公开(公告)号：US08751714B2

公开(公告)日：2014-06-10

申请号：US12889777

申请日：2010-09-24

申请人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

发明人： Robert J. Safranek ,  Debendra Das Sharma ,  Ganapati N. Srinivasa

IPC分类号： G06F13/42

CPC分类号： G06F12/0835

摘要： Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.

摘要翻译： 通过PCIe接口实现Intel QuickPathInterconnect®（QPI）协议的方法和设备。 通过使用QPI数据位映射到相应的PCIe x16，x8和x4通道配置，QPI协议的上层通过PCIe接口的物理层实现。 采用QPI链路层到PCIe物理层接口从底层PCIe物理层（和相应的PCIe接口电路）抽取QPI链路，路由和协议层，从而使QPI协议消息能够在PCIe硬件上采用。 因此，诸如支持相干存储器事务的QPI功能可以通过PCIe接口电路来实现。

公开(公告)号：US20140189299A1

公开(公告)日：2014-07-03

申请号：US13730565

申请日：2012-12-28

申请人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

发明人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC分类号： G06F9/38

CPC分类号： G06F9/3891

摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

摘要翻译： 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏一组小型物理处理器核心。

公开(公告)号：US06618046B1

公开(公告)日：2003-09-09

申请号：US09675610

申请日：2000-09-29

申请人： Ganapati N. Srinivasa ,  Gopalan Ramanujam ,  Glenn M. Lewis ,  Calvin J. Lin ,  Jeffrey A. Larson ,  Arunachalam S. Prakash

发明人： Ganapati N. Srinivasa ,  Gopalan Ramanujam ,  Glenn M. Lewis ,  Calvin J. Lin ,  Jeffrey A. Larson ,  Arunachalam S. Prakash

IPC分类号： G06T1700

CPC分类号： G06T15/00 ,  G06Q30/0283 ,  G06T17/00

摘要： A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

摘要翻译： 提供了一种渲染成本估算方法，用于生成如果计算机生成的图像实际上从计算机图形模型呈现的情况下足以接近实际渲染成本的渲染成本估计。 确定影响实际渲染成本的多个成本因素。 计算机图形模型导出了代表性信息，包括成本估算参数，充分表征成本因素。 估计参数与渲染成本估算关系相结合，表示成本因素对渲染成本的影响。 基于从计算机图形模型导出的估计参数和估计关系来生成渲染成本估计。

公开(公告)号：US20140223226A1

公开(公告)日：2014-08-07

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/14

CPC分类号： G06F11/1405 ,  G06F11/1064

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

摘要翻译： 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：US20140189301A1

公开(公告)日：2014-07-03

申请号：US13730800

申请日：2012-12-28

申请人： Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Ganapati N. Srinivasa ,  Eliezer Weissmann ,  Guarav Khanna ,  Mishali Naik ,  Russell J. Fenger ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy ,  David A. Koufaty ,  Paolo Narvaez

发明人： Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Ganapati N. Srinivasa ,  Eliezer Weissmann ,  Guarav Khanna ,  Mishali Naik ,  Russell J. Fenger ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy ,  David A. Koufaty ,  Paolo Narvaez

IPC分类号： G06F15/80

CPC分类号： G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/22

摘要： A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

摘要翻译： 一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。 迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元件迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下方式确定是否允许基于 评估性能好处。 可用的能源和热力预算评估逻辑是评估可用的能源和热力预算，并确定如果迁移符合可用能源和热预算，则允许迁移。 工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

公开(公告)号：US20140189297A1

公开(公告)日：2014-07-03

申请号：US13730491

申请日：2012-12-28

申请人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Gaurav Khanna ,  Russell J. Fenger ,  Bryant E. Bigbee ,  Andrew D. Henroid

发明人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Gaurav Khanna ,  Russell J. Fenger ,  Bryant E. Bigbee ,  Andrew D. Henroid

IPC分类号： G06F15/76

CPC分类号： G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

摘要翻译： 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。

公开(公告)号：US20140181830A1

公开(公告)日：2014-06-26

申请号：US13997811

申请日：2012-12-26

申请人： Mishali Naik ,  Ganapati N. Srinivasa ,  Alon Naveh ,  Inder M. Sodhi ,  Paolo Narvaez ,  Eugene Gorbatov ,  Eliezer Weissmann ,  Andrew D. Henroid ,  Andrew J. Herdrich ,  Guarav Khanna ,  Scott D. Hahn ,  Paul Brett ,  David A. Koufaty ,  Dheeraj R. Subbareddy ,  Abirami Prabhakaran

发明人： Mishali Naik ,  Ganapati N. Srinivasa ,  Alon Naveh ,  Inder M. Sodhi ,  Paolo Narvaez ,  Eugene Gorbatov ,  Eliezer Weissmann ,  Andrew D. Henroid ,  Andrew J. Herdrich ,  Guarav Khanna ,  Scott D. Hahn ,  Paul Brett ,  David A. Koufaty ,  Dheeraj R. Subbareddy ,  Abirami Prabhakaran

IPC分类号： G06F9/50

CPC分类号： G06F9/461 ,  G06F9/3851 ,  G06F9/4856 ,  G06F9/5094 ,  Y02D10/22

摘要： According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.

摘要翻译： 根据一个实施例，处理器包括用于执行多个线程的多个处理器核心，通信地耦合到所述多个处理器核心的共享存储器，通信地耦合到所述多个处理器的功率控制单元（PCU），以便在没有 如果由第一处理器核心执行的线程应该迁移到第二处理器核心的任何软件（SW）干预，以及迁移单元，响应于接收到来自PCU的指令来迁移线程，以存储至少一个 共享存储器中的第一处理器核心的架构状态的一部分，并且将线程迁移到第二处理器核心，而没有任何SW干预，使得第二处理器核心可以基于来自共享存储器的架构状态继续执行线程，而没有 SW的知识。

公开(公告)号：US06897857B2

公开(公告)日：2005-05-24

申请号：US10444855

申请日：2003-05-22

申请人： Ganapati N. Srinivasa ,  Gopalan Ramanujam ,  Glenn M. Lewis ,  Calvin J. Lin ,  Jeffrey A. Larson ,  Arunachalam S. Prakash

发明人： Ganapati N. Srinivasa ,  Gopalan Ramanujam ,  Glenn M. Lewis ,  Calvin J. Lin ,  Jeffrey A. Larson ,  Arunachalam S. Prakash

IPC分类号： G06T15/00 ,  G06T17/00

CPC分类号： G06T15/00 ,  G06Q30/0283 ,  G06T17/00

摘要： A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

摘要翻译： 提供了一种渲染成本估算方法，用于生成如果计算机生成的图像实际上从计算机图形模型呈现的情况下足以接近实际渲染成本的渲染成本估计。 确定影响实际渲染成本的多个成本因素。 计算机图形模型导出了代表性信息，包括成本估算参数，充分表征成本因素。 估计参数与渲染成本估算关系相结合，表示成本因素对渲染成本的影响。 基于从计算机图形模型导出的估计参数和估计关系来生成渲染成本估计。