公开(公告)号：US09448879B2

公开(公告)日：2016-09-20

申请号：US13994105

申请日：2011-12-22

Applicant: Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

Inventor： Theodros Yigzaw ,  Oded Lempel ,  Hisham Shafi ,  Geeyarpuram N. Santhanakrishnan ,  Jose A. Vargas ,  Ganapati N Srinivasa ,  Mohan J Kumar ,  Larisa Novakovsky ,  Lihu Rappoport ,  Chen Koren ,  Julius Mandelblat ,  Michael Mishaeli

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1407

Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Abstract translation: 描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。 例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

公开(公告)号：US20140223226A1

公开(公告)日：2014-08-07

申请号：US13994609

申请日：2011-12-22

Applicant: Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14

CPC classification number: G06F11/1405 ,  G06F11/1064

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract translation: 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：US20140189261A1

公开(公告)日：2014-07-03

申请号：US13729439

申请日：2012-12-28

Applicant: GUR HILDESHEIM ,  SHLOMO RAIKIN ,  ITTAI ANATI ,  GIDEON GERZON ,  HISHAM SHAFI ,  ALEX BERENZON ,  GEOFFREY S. STRONGIN ,  IRIS SORANI

Inventor： GUR HILDESHEIM ,  SHLOMO RAIKIN ,  ITTAI ANATI ,  GIDEON GERZON ,  HISHAM SHAFI ,  ALEX BERENZON ,  GEOFFREY S. STRONGIN ,  IRIS SORANI

IPC: G06F12/14

CPC classification number: G06F12/1027 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1052

Abstract: A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

Abstract translation: 一方面的处理器包括操作模式检查逻辑，用于基于用于指示尝试访问是否由片上处理器逻辑的操作模式来确定是否允许尝试访问操作模式和访问类型受保护存储器。 访问类型检查逻辑是基于尝试访问操作模式和访问类型受保护的存储器的访问类型来确定是否允许尝试访问操作模式和访问类型受保护的存储器。 保护逻辑与操作模式检查逻辑耦合，并与访问类型检查逻辑耦合。 如果操作模式检查逻辑和访问类型检查逻辑中的至少一个确定不允许尝试访问，则保护逻辑是拒绝尝试访问操作模式和访问类型保护的存储器。

公开(公告)号：US20140281457A1

公开(公告)日：2014-09-18

申请号：US13854001

申请日：2013-03-29

Applicant: Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

Inventor： Elierzer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract translation: 描述异构处理器架构和启动异构处理器的方法。 根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。 引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

公开(公告)号：US20140189274A1

公开(公告)日：2014-07-03

申请号：US13730563

申请日：2012-12-28

Applicant: Gur Hildesheim ,  Ittai Anati ,  Hisham Shafi ,  Shlomo Raikin ,  Gideon Gerzon ,  Uday R Savagaonkar ,  Carlos V Rozas ,  Francis X McKeen ,  Michael A Goldsmith ,  Dewan Prashant

Inventor： Gur Hildesheim ,  Ittai Anati ,  Hisham Shafi ,  Shlomo Raikin ,  Gideon Gerzon ,  Uday R Savagaonkar ,  Carlos V Rozas ,  Francis X McKeen ,  Michael A Goldsmith ,  Dewan Prashant

IPC: G06F12/14

CPC classification number: G06F12/145 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/1483 ,  G06F21/53

Abstract: An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.

Abstract translation: 一种用于由处理器管理保护表的装置和方法。 例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑以管理保护表，所述保护表具有用于每个受保护页面的条目或存储器中每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

Applicant: Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.