专利检索 ap:("Mishali Naik" OR "Ganapati N. Srinivasa" OR "Alon Naveh" OR "Inder M. Sodhi" OR "Paolo Narvaez" OR "Eugene Gorbatov" OR "Eliezer Weissmann" OR "Andrew D. Henroid" OR "Andrew J. Herdrich" OR "Guarav Khanna" OR "Scott D. Hahn" OR "Paul Brett" OR "David A. Koufaty" OR "Dheeraj R. Subbareddy" OR "Abirami Prabhakaran") AND inv:"Andrew D. Henroid" 第 1 页

1.

发明申请
THREAD MIGRATION SUPPORT FOR ARCHITECTUALLY DIFFERENT CORES 审中-公开
标题翻译：用于建筑物不同角度的螺纹移动支撑

公开(公告)号：US20140181830A1

公开(公告)日：2014-06-26

申请号：US13997811

申请日：2012-12-26

申请人： Mishali Naik , Ganapati N. Srinivasa , Alon Naveh , Inder M. Sodhi , Paolo Narvaez , Eugene Gorbatov , Eliezer Weissmann , Andrew D. Henroid , Andrew J. Herdrich , Guarav Khanna , Scott D. Hahn , Paul Brett , David A. Koufaty , Dheeraj R. Subbareddy , Abirami Prabhakaran

发明人： Mishali Naik , Ganapati N. Srinivasa , Alon Naveh , Inder M. Sodhi , Paolo Narvaez , Eugene Gorbatov , Eliezer Weissmann , Andrew D. Henroid , Andrew J. Herdrich , Guarav Khanna , Scott D. Hahn , Paul Brett , David A. Koufaty , Dheeraj R. Subbareddy , Abirami Prabhakaran

IPC分类号： G06F9/50

CPC分类号： G06F9/461 , G06F9/3851 , G06F9/4856 , G06F9/5094 , Y02D10/22

摘要： According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.

摘要翻译： 根据一个实施例，处理器包括用于执行多个线程的多个处理器核心，通信地耦合到所述多个处理器核心的共享存储器，通信地耦合到所述多个处理器的功率控制单元（PCU），以便在没有如果由第一处理器核心执行的线程应该迁移到第二处理器核心的任何软件（SW）干预，以及迁移单元，响应于接收到来自PCU的指令来迁移线程，以存储至少一个共享存储器中的第一处理器核心的架构状态的一部分，并且将线程迁移到第二处理器核心，而没有任何SW干预，使得第二处理器核心可以基于来自共享存储器的架构状态继续执行线程，而没有 SW的知识。

2.

发明申请
METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRIC CORE VIEW 有权
标题翻译：用于打造异质系统并提供对称核心视图的方法

公开(公告)号：US20140281457A1

公开(公告)日：2014-09-18

申请号：US13854001

申请日：2013-03-29

申请人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy

发明人： Elierzer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy

IPC分类号： G06F9/44

CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36

摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

摘要翻译： 描述异构处理器架构和启动异构处理器的方法。根据一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 以及一个包装单元，用于启用自举处理器。引导处理器初始化同构物理处理器内核，而异构处理器将均匀处理器的外观呈现给系统固件界面。

3.

发明申请
HETERGENEOUS PROCESSOR APPARATUS AND METHOD 有权
标题翻译：空气处理器装置和方法

公开(公告)号：US20140189297A1

公开(公告)日：2014-07-03

申请号：US13730491

申请日：2012-12-28

申请人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Gaurav Khanna , Russell J. Fenger , Bryant E. Bigbee , Andrew D. Henroid

发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Gaurav Khanna , Russell J. Fenger , Bryant E. Bigbee , Andrew D. Henroid

IPC分类号： G06F15/76

CPC分类号： G06F9/45558 , G06F9/3885 , G06F9/5077 , G06F2009/4557

摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

摘要翻译： 描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。

4.

发明申请
HIGH DYNAMIC RANGE SOFTWARE-TRANSPARENT HETEROGENEOUS COMPUTING ELEMENT PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：高动态范围软件 - 透明异构计算元件处理器，方法和系统

公开(公告)号：US20140189301A1

公开(公告)日：2014-07-03

申请号：US13730800

申请日：2012-12-28

申请人： Eugene Gorbatov , Alon Naveh , Inder M. Sodhi , Ganapati N. Srinivasa , Eliezer Weissmann , Guarav Khanna , Mishali Naik , Russell J. Fenger , Andrew D. Henroid , Dheeraj R. Subbareddy , David A. Koufaty , Paolo Narvaez

发明人： Eugene Gorbatov , Alon Naveh , Inder M. Sodhi , Ganapati N. Srinivasa , Eliezer Weissmann , Guarav Khanna , Mishali Naik , Russell J. Fenger , Andrew D. Henroid , Dheeraj R. Subbareddy , David A. Koufaty , Paolo Narvaez

IPC分类号： G06F15/80

CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/22

摘要： A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

摘要翻译： 一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元件迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下方式确定是否允许基于评估性能好处。可用的能源和热力预算评估逻辑是评估可用的能源和热力预算，并确定如果迁移符合可用能源和热预算，则允许迁移。工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

5.

发明申请
RESCHEDULING WORKLOADS TO ENFORCE AND MAINTAIN A DUTY CYCLE 有权
标题翻译：减少执行和维护一个占空比的工作量

公开(公告)号：US20150169036A1

公开(公告)日：2015-06-18

申请号：US14109388

申请日：2013-12-17

申请人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh

发明人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh

IPC分类号： G06F1/32 , G06F9/48

CPC分类号： G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24 , Y02D50/20

摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。描述和要求保护其他实施例。

6.

发明申请
COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT 有权

公开(公告)号：US20130275796A1

公开(公告)日：2013-10-17

申请号：US13976507

申请日：2011-12-30

申请人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

发明人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

IPC分类号： G06F1/28

CPC分类号： G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172

摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

7.

发明申请
COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT 有权

公开(公告)号：US20130275737A1

公开(公告)日：2013-10-17

申请号：US13976520

申请日：2011-12-30

申请人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

发明人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

IPC分类号： G06F9/445

CPC分类号： G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172

摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

8.

发明授权
Collaborative processor and system performance and power management 有权
标题翻译：协同处理器和系统性能和电源管理

公开(公告)号：US09442739B2

公开(公告)日：2016-09-13

申请号：US13976507

申请日：2011-12-30

申请人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

发明人： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann

IPC分类号： G06F1/00 , G06F11/30 , G06F9/44 , G06F17/30 , G06F9/445 , G06F1/28 , G06F1/32 , G06F11/36 , G06F1/26 , G06F9/22 , G06F11/34

CPC分类号： G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172

摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

摘要翻译： 本发明涉及一种平台电源管理方案。在一些实施例中，平台使用OSPM系统请求的一个或多个参数来提供相对性能量表。

9.

发明申请
MANAGING PERFORMANCE POLICIES BASED ON WORKLOAD SCALABILITY 有权
标题翻译：基于工作流程可扩展性管理绩效政策

公开(公告)号：US20140189694A1

公开(公告)日：2014-07-03

申请号：US13728327

申请日：2012-12-27

申请人： Paul S. Diefenbaugh , Andrew D. Henroid , Eliezer Weissmann , Krishnakanth V. Sistla

发明人： Paul S. Diefenbaugh , Andrew D. Henroid , Eliezer Weissmann , Krishnakanth V. Sistla

IPC分类号： G06F9/48

CPC分类号： G06F9/5094 , G06F1/3203 , Y02D10/22

摘要： Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.

摘要翻译： 方法和系统可以提供用于识别与平台相关联的工作负载并确定工作负载的可扩展性。此外，可以至少部分地基于工作负载的可扩展性来管理平台的性能策略。在一个示例中，确定可伸缩性包括确定生产周期与实际周期的比率。