公开(公告)号：US20090125763A1

公开(公告)日：2009-05-14

申请号：US11939282

申请日：2007-11-13

Applicant: Yeong-Jar Chang ,  Chung-Fu Lin

Inventor： Yeong-Jar Chang ,  Chung-Fu Lin

IPC: G11C29/08 ,  G06F11/26

CPC classification number: G11C29/16 ,  G01R31/318552 ,  G06F11/2215 ,  G11C29/12015 ,  G11C29/14

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract translation: 提供了可编程存储器内置自检电路及其时钟切换电路。 存储器内置的自检电路能够提供用户预设的更多自检功能，简化了现有技术中的冗余电路，并通过指令解码器和内置的降低芯片面积和降低成本 自检控制器。 本发明还提供了一些存储器的外围控制电路。 控制电路占用的面积较小，能够更灵活地测试存储器。 本发明还提供一种能够在不同时钟速度下正确测试芯片的时钟切换电路，这有利于提高嵌入在芯片中的存储器的可测试性和可分析性，从而增加故障覆盖。

公开(公告)号：US20070255986A1

公开(公告)日：2007-11-01

申请号：US11819464

申请日：2007-06-27

Applicant: Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

Inventor： Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

IPC: G01R31/28

CPC classification number: G01R31/318555

Abstract: A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.

Abstract translation: 提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。 控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。 包装测试电路包括解码逻辑和多个封装边界寄存器。 解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。 与现有技术相比，测试时间缩短。

公开(公告)号：US20060064618A1

公开(公告)日：2006-03-23

申请号：US11001345

申请日：2004-11-30

Applicant: Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

Inventor： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

IPC: G01R31/28

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/72 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

Abstract translation: 本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。 它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。 基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。 它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重构电路。 本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。 它还增加了修复率，并减少了所需的面积开销。

公开(公告)号：US20100257415A1

公开(公告)日：2010-10-07

申请号：US12416646

申请日：2009-04-01

Applicant: Chung-Fu Lin ,  Yeong-Jar Chang

Inventor： Chung-Fu Lin ,  Yeong-Jar Chang

IPC: G11C29/12 ,  G06F11/22 ,  G06F12/02

CPC classification number: G11C29/16 ,  G11C29/20 ,  G11C2029/0401

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract translation: 提供了基于指令的可编程存储器内置自测（P-MBIST）电路及其地址发生器。 P-MBIST电路根据由外部自动测试设备（ATE）提供的紧凑测试指令的解码产生控制信号。 地址生成器根据控制信号产生存储器地址。 控制信号和存储器地址被发送到嵌入式存储器以执行MBIST。 P-MBIST电路和地址发生器的算法特定设计使得它们能够以全时钟速度支持多种测试算法，并占用更小的芯片面积。

公开(公告)号：US20090271133A1

公开(公告)日：2009-10-29

申请号：US12108796

申请日：2008-04-24

Applicant: Jung-Chi Ho ,  Sheng-Bin Lin ,  Yeong-Jar Chang

Inventor： Jung-Chi Ho ,  Sheng-Bin Lin ,  Yeong-Jar Chang

IPC: G01R23/00

CPC classification number: G01R29/26 ,  G01R31/3016 ,  G01R31/31709

Abstract: Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.

Abstract translation: 提供了一种用于测量时钟信号的抖动的测量电路。 延迟元件将时钟信号延迟到延迟的时钟信号。 锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。 基于锁存器的锁存结果，有限状态机产生用于控制延迟元件的控制信号。 如果锁存结果指示时钟信号的转换边缘不在窗口值内，则控制信号调整延迟元件的延迟和窗口值。 基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

公开(公告)号：US07564285B2

公开(公告)日：2009-07-21

申请号：US11754783

申请日：2007-05-29

Applicant: Chia-Wei Chang ,  Yeong-Jar Chang

Inventor： Chia-Wei Chang ,  Yeong-Jar Chang

IPC: H03H11/26

CPC classification number: H03H11/265

Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

Abstract translation: 可控延迟线包括抗抖动单元，依赖电流源，第一电流镜，第二电流镜，调节电容器，补偿电容器和输出缓冲器单元。 抗抖动单元接收第一偏置电压并且基于第一偏置电压产生第二偏置电压。 当在可控延迟线中使用的电压源具有变化时，第二偏置电压随之变化。 调节电容器用于减小电压源与第一电流源的节点电压之间的电压差的变化。 补偿电容器用于减小输出缓冲器单元的输入信号对节点电压的转变的影响，以便降低输出缓冲器单元的输出信号的抖动量。

公开(公告)号：US20070040596A1

公开(公告)日：2007-02-22

申请号：US11285007

申请日：2005-11-23

Applicant: Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

Inventor： Yow-Tyng Nieh ,  Sheng-Yu Hsu ,  Shih-Hsu Huang ,  Yeong-Jar Chang

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract translation: 我们提出了用于峰值电流降低的反相方案。 基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段 时钟源。 因此，我们的方法可以有效地降低时钟树的峰值电流。 该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

公开(公告)号：US06937106B2

公开(公告)日：2005-08-30

申请号：US10749560

申请日：2004-01-02

Applicant: Yeong-Jar Chang ,  Shen-Tien Lin ,  Wen-Ching Wu ,  Kun-Lun Luo

Inventor： Yeong-Jar Chang ,  Shen-Tien Lin ,  Wen-Ching Wu ,  Kun-Lun Luo

IPC: G01R29/26 ,  H03L7/06 ,  G01R23/00

CPC classification number: G01R29/26 ,  H03L7/06

Abstract: A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.

Abstract translation: 公开了一种用于VCO（压控振荡器）和PLL（锁相环）的内置抖动测量电路。 该电路包括用于分频信号的分频器，用于将分频信号的周期转换为数字值的时间数字转换器（TDC），用于计算分频信号周期的方差的方差计算器，用于 计算分割信号的周期的平均值，用于编码和计算分频信号的周期的编码器和计数器，以及作为所有其他分量的控制器的状态控制器。 所公开的电路利用要测量的开环电路的输出时钟和用于增加原始信号的抖动的分频器。 通过测量闭环电路的带宽，相应地，通过将​​测量的带宽与来自外推的抖动值相关联来测量开环或闭环电路的输出时钟的抖动。

公开(公告)号：US20090072869A1

公开(公告)日：2009-03-19

申请号：US11854560

申请日：2007-09-13

Applicant: Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

Inventor： Jen-Chien Hsu ,  Hung-Wen Lu ,  Chau-Chin Su ,  Yeong-Jar Chang

IPC: G11C27/02

CPC classification number: G11C27/024 ,  G11C27/026

Abstract: Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

Abstract translation: 公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

公开(公告)号：US07506231B2

公开(公告)日：2009-03-17

申请号：US11819464

申请日：2007-06-27

Applicant: Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

Inventor： Yeong-Jar Chang ,  Wen-Ching Wu ,  Kun-Lun Luo ,  Chia-Jen Lee

IPC: G01R31/28 ,  G11C29/00

CPC classification number: G01R31/318555

Abstract: A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.

Abstract translation: 提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。 控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。 包装测试电路包括解码逻辑和多个封装边界寄存器。 解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。 与现有技术相比，测试时间缩短。