公开(公告)号：US08423343B2

公开(公告)日：2013-04-16

申请号：US13011942

申请日：2011-01-24

申请人： Meng-Huan Wu ,  Ren-Song Tsay

发明人： Meng-Huan Wu ,  Ren-Song Tsay

IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F13/10 ,  G06F13/12

CPC分类号： G06F17/5022 ,  G06F9/52 ,  G06F2217/68

摘要： The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

摘要翻译： 本发明公开了一种用于多核指令集仿真的高并行同步方法。 所提出的方法利用并行编译的MCISS的新的分布式调度机制。 所提出的方法可以增强MCISS的并行性，从而可以有效利用多核主机的计算能力。 利用本发明的预测方法的分布式调度大大缩短了ISS花费在同步上的等待时间。

公开(公告)号：US20130054854A1

公开(公告)日：2013-02-28

申请号：US13398083

申请日：2012-02-16

申请人： Mao-Lin Li ,  Chen-Kang Lo ,  Li-Chun Chen ,  Hong-Jie Huang ,  Jen-Chieh Yeh ,  Ren-Song Tsay

发明人： Mao-Lin Li ,  Chen-Kang Lo ,  Li-Chun Chen ,  Hong-Jie Huang ,  Jen-Chieh Yeh ,  Ren-Song Tsay

IPC分类号： G06F13/362

CPC分类号： G06F13/362 ,  G06F13/1642

摘要： The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.

摘要翻译： 本发明提出了一种有效的循环计数精确交易级别（CCA-TLM）全总线建模和仿真技术。 使用两相仲裁器和主从模型，提出了基于FSM的复合主从从对和仲裁器事务（CMSAT）模型，用于高效和准确的动态模拟。 这种方法对于复杂的多处理器片上系统（MPSoC）设计的总线架构探索和竞争分析特别有效。

公开(公告)号：US08336001B2

公开(公告)日：2012-12-18

申请号：US12913674

申请日：2010-10-27

申请人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

发明人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

摘要翻译： 一种用于制造集成电路（IC）的方法和装置，所述方法包括：通过图形构造单元生成与所述IC的第一网络对应的第一图形，所述第一图形表示所述第一网络的针脚作为顶点 以及第一网的两个引脚之间的连接作为边缘，第一图形还对应于第一IC布局; 识别第一图中的第一和第二对未连接顶点，分别插入第一和第二冗余边缘，第一冗余边缘和第二冗余边缘分别形成第一连接环路和第二连接环路，每个环路 还包括所述第一图形的至少两个边缘; 计算第一冗余边缘和第二冗余边缘的容差比; 根据其容差比对第一和第二冗余边进行排序; 计算与插入具有最高容差比的第一或第二冗余边缘之一相关联的第一IC布局的产出率变化，以及如果产出率变化较大，则更新第一IC布局以包括具有最高容差比的冗余边缘 比零; 以及计算与插入具有第二高容差比的第一或第二冗余边缘相关联的第一IC布局的产出率变化，并且如果产出率变化为更新，则将第一IC布局更新为包括具有第二高容差比的冗余边缘 大于零。

公开(公告)号：US5461576A

公开(公告)日：1995-10-24

申请号：US115995

申请日：1993-09-01

申请人： Ren-Song Tsay ,  Chwen-Cher Chang

发明人： Ren-Song Tsay ,  Chwen-Cher Chang

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F17/00

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： An electronic design automation tool embodiment uses a single slack graph structure throughout a process to provide communication between a placer (performing placement) and a timing constraint generator (performing slack distribution). The tool includes a slack graph generator, a timing calculator, a timing analyzer, a timing constraint generator and a net bounding box generator. A list of net constraints and a list of complete path constraints are fed to the slack graph generator during operation. Timing calculations from the delay calculator and zero net RC delays from a clustering process in a placer also provide input to the slack graph generator. The list of net constraints, a list of pin-to-pin constraints and a set of specifications for system clocking are input to the timing analyzer. The timing constraint generator receives a composite slack graph from the timing calculator, slack graph generator and timing analyzer. A refined slack graph is output to the net timing constraint generator for mincut placement and placement on an iterative basis. The net timing constraint can be presented in many format, such as limit on net bounding box.

摘要翻译： 电子设计自动化工具实施例在整个过程中使用单个松弛图形结构来提供放置器（执行放置）和定时约束生成器之间的通信（执行松弛分布）。 该工具包括一个松弛图发生器，一个定时计算器，一个定时分析器，一个定时约束发生器和一个净边界框发生器。 在操作期间，将净约束列表和完整路径约束列表馈送到松弛图生成器。 来自延迟计算器的定时计算和零网RC延迟从放样器中的聚类过程也为松弛图生成器提供输入。 网络限制列表，引脚对引脚限制列表和系统时钟的一组规范输入到时序分析器。 定时约束生成器从定时计算器，松弛图发生器和定时分析器接收复合松弛图。 精简的松弛图被输出到净时间约束发生器，以便在迭代的基础上进行最小化的位置和放置。 净时序约束可以以许多格式呈现，例如网边界限制。

公开(公告)号：US08407647B2

公开(公告)日：2013-03-26

申请号：US12970888

申请日：2010-12-16

申请人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

发明人： Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

摘要翻译： 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 从这些估计，该方法准确地估计所需的水平和垂直路由资源之间的比例，称为H / V需求比率。 根据H / V需求比，可以确定块的高度和宽度的准确估计。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

公开(公告)号：US20110154282A1

公开(公告)日：2011-06-23

申请号：US12970888

申请日：2010-12-16

申请人： Fong-Yuan CHANG ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

发明人： Fong-Yuan CHANG ,  Sheng-Hsiung Chen ,  Tung-Chieh Chen ,  Ren-Song Tsay ,  Wai-Kei Mak

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081

摘要： A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

摘要翻译： 描述了一种用于设计和制造集成电路的方法。 该方法使用线段的统计模型来精确估计块内最小长度正交线段的预期长度。 根据这些估计，该方法精确地估计所需的水平和垂直路由资源之间的比例，称为“H / V需求比”。从H / V需求比率来看，块的高度和宽度的准确估计可以是 决心。 此后，可以快速且准确地执行放置和布线，从而允许块被快速且成本有效地设计和制造。 还描述了一种设计具有有效的金属-1资源利用的集成电路的方法。

公开(公告)号：US20110107278A1

公开(公告)日：2011-05-05

申请号：US12913674

申请日：2010-10-27

申请人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

发明人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

摘要翻译： 一种用于制造集成电路（IC）的方法和装置，所述方法包括：通过图形构造单元生成与所述IC的第一网络对应的第一图形，所述第一图形表示所述第一网络的针脚作为顶点 以及第一网的两个引脚之间的连接作为边缘，第一图形还对应于第一IC布局; 识别第一图中的第一和第二对未连接顶点，分别插入第一和第二冗余边缘，第一冗余边缘和第二冗余边缘分别形成第一连接环路和第二连接环路，每个环路 还包括所述第一图形的至少两个边缘; 计算第一冗余边缘和第二冗余边缘的容差比; 根据其容差比对第一和第二冗余边进行排序; 计算与插入具有最高容差比的第一或第二冗余边缘之一相关联的第一IC布局的产出率变化，以及如果产出率变化较大，则更新第一IC布局以包括具有最高容差比的冗余边缘 比零; 以及计算与插入具有第二高容差比的第一或第二冗余边缘相关联的第一IC布局的产出率变化，并且如果产出率变化为更新，则将第一IC布局更新为包括具有第二高容差比的冗余边缘 大于零。

公开(公告)号：US6134516A

公开(公告)日：2000-10-17

申请号：US19384

申请日：1998-02-05

申请人： Steven Wang ,  Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Ren-Song Tsay ,  Richard Yachyang Sun ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai

发明人： Steven Wang ,  Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Ren-Song Tsay ,  Richard Yachyang Sun ,  Quincy Kun-Hsu Shen ,  Mike Mon Yen Tsai

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022 ,  G06F17/5027

摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.

摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。 在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。 这些模式的核心是控制该系统整体运行的软件内核。 内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环 只要存在有效的测试台过程。 根据本发明的实施例的仿真服务器允许多个用户访问相同的可重配置硬件单元，以在网络和非网络环境中以时间共享的方式有效地模拟和加速相同或不同的用户设计。 服务器提供多个用户或进程来访问可重新配置的硬件单元，以实现加速和硬件状态交换的目的。 模拟服务器包括调度程序，一个或多个设备驱动程序和可重新配置的硬件单元。 模拟服务器中的调度器基于抢占式循环算法。 服务器调度程序包括模拟作业队列表，优先级排序器和作业交换器。

公开(公告)号：US6009256A

公开(公告)日：1999-12-28

申请号：US850136

申请日：1997-05-02

申请人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Richard Yachyang Sun ,  Mike Mon Yen Tsai ,  Ren-Song Tsay ,  Steven Wang

发明人： Ping-Sheng Tseng ,  Sharon Sheau-Pyng Lin ,  Quincy Kun-Hsu Shen ,  Richard Yachyang Sun ,  Mike Mon Yen Tsai ,  Ren-Song Tsay ,  Steven Wang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5027 ,  G06F17/5022

摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.