公开(公告)号：US5699298A

公开(公告)日：1997-12-16

申请号：US718525

申请日：1996-10-07

申请人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Yuan-Chang Liu ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Han Sung Chen ,  Fuchia Shone

发明人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Yuan-Chang Liu ,  Chun-Hsiung Hung ,  Weitong Chuang ,  Han Sung Chen ,  Fuchia Shone

IPC分类号： G11C16/16 ,  G11C16/30 ,  G11C16/00

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/30

摘要： Substantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.

摘要翻译： PCT No.PCT / US96 / 07490 Sec。 371日期1996年10月7日第 102（e）1996年10月7日PCT 1996年5月22日提交闪速存储器件的擦除过程中遇到的峰值电流的实质性降低是通过根据预期的带 - 带来在擦除期间选择源极电压电位来实现的 过程中遇到的隧道电流。 在该过程开始时，选择较低的源极电压电位，其足够高以引起显着擦除，同时抑制阵列的一部分中的带间隧穿电流，并且在擦除处理的第二部分期间， 利用更高的源极电位，确保阵列的成功擦除，而不超过与器件一起使用的电源的峰值电流要求。 擦除序列的第一部分和第二部分除了Fowler-Nordheim隧道电流之外还将引起带间隧穿电流。 带 - 带隧穿电流的特征在于开启阈值源极电位，其与接收电压序列的电池的阈值成反比。 在擦除序列的第一部分中使用的源电压被设置为接近或高于处于高阈值状态的较高阈值电池的阈值源极电位的接通或高于电平，但小于阈值源电位的导通电平较低 阈值细胞处于高阈值状态。 第二部分中的源极电位被设置在接近或高于阈值电位的阈值源电位的接通或高于在高阈值状态下的较低阈值电池的电位。

公开(公告)号：US08717813B2

公开(公告)日：2014-05-06

申请号：US13308266

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C11/34

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US08643404B1

公开(公告)日：2014-02-04

申请号：US13556579

申请日：2012-07-24

申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H03K3/00

CPC分类号： H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

摘要翻译： 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟 输出缓冲区延迟。

公开(公告)号：US20130242665A1

公开(公告)日：2013-09-19

申请号：US13536555

申请日：2012-06-28

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

摘要翻译： 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US20130094319A1

公开(公告)日：2013-04-18

申请号：US13708150

申请日：2012-12-07

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。

公开(公告)号：US20120327722A1

公开(公告)日：2012-12-27

申请号：US13523060

申请日：2012-06-14

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 集成电路包括串行外设接口存储器件。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20120268987A1

公开(公告)日：2012-10-25

申请号：US13539831

申请日：2012-07-02

申请人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.

摘要翻译： 一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。 如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。

公开(公告)号：US20120262988A1

公开(公告)日：2012-10-18

申请号：US13308301

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C16/10

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。 该装置还包括执行泄漏抑制处理的控制器。 泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。 在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

公开(公告)号：US08238162B2

公开(公告)日：2012-08-07

申请号：US12868228

申请日：2010-08-25

申请人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.

摘要翻译： 一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。 如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。

公开(公告)号：US20110238939A1

公开(公告)日：2011-09-29

申请号：US13155404

申请日：2011-06-08

申请人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/14

CPC分类号： G11C8/20 ,  G06F21/79 ,  G11C16/22

摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

摘要翻译： 存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。 存储器阵列包含许多存储器块。 状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。 状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。 安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。