公开(公告)号：US20080161073A1

公开(公告)日：2008-07-03

申请号：US11889355

申请日：2007-08-10

申请人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong Woo Lee

发明人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong Woo Lee

IPC分类号： H04B1/38

CPC分类号： H04B1/1607

摘要： Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.

摘要翻译： RFIC的实施例和用于相同和移动终端的方法可以在内部减小输入电压以向射频收发器提供规定的电压。 RFIC的实施例可以具有高效率和/或低噪声。 在一个实施例中，设备可以包括PMIC和RFIC。 RFIC可以包括用于执行RF传输和RF接收的RF收发器，用于降低由PMIC提供的电压的DC-DC转换器和LDO调节器，以将降低的电压调节到由RF收发器使用的固定电压 。

公开(公告)号：US20060003720A1

公开(公告)日：2006-01-05

申请号：US11057414

申请日：2005-02-15

申请人： Kang Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B1/40 ,  H04B1/06 ,  H04B7/00

CPC分类号： H03L7/085 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/199

摘要： An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

公开(公告)号：US07560960B2

公开(公告)日：2009-07-14

申请号：US11902358

申请日：2007-09-20

申请人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong-Woo Lee

发明人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong-Woo Lee

IPC分类号： H03B21/00

CPC分类号： H03L7/23 ,  H03L7/183 ,  H03L7/1976

摘要： The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

摘要翻译： 本申请公开了与频率合成器相关的系统和方法实施例。 频率合成器的实施例可以具有低相位噪声和窄通道间隔。 频率合成器的实施例可以使用两个锁相环。 频率合成器的一个实施例可以包括：参考频率振荡器，用于输出具有参考频率的信号，整数N个锁相环，以基于参考频率信号产生第一输出频率信号;分数N相锁相环 基于参考频率信号产生第二输出频率，以及通过组合第一输出频率和第二输出频率来产生输出频率信号的电路。

公开(公告)号：US07512390B2

公开(公告)日：2009-03-31

申请号：US11057414

申请日：2005-02-15

申请人： Kang Yoon Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang Yoon Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B7/00 ,  H04B1/181

CPC分类号： H03L7/085 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/199

摘要： An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

摘要翻译： LC-VCO包括输出频率信号的多谐振荡器，将频率信号调谐第一量的微调电路，将频率信号调谐第二量的粗调谐电路，以及控制电路， 粗调电路。 粗调谐电路由一个或多个电容阵列形成，并且微调电路由一个或多个变容二极管形成。 电容阵列优选地由数字信号控制，其中每个位选择性地将相应的电容器耦合到多谐振荡器。 模拟信号控制变容二极管的值。 电容阵列和变容二极管对多谐振荡器中的感应器充电和放电，以调谐频率信号。 VCO可以并入在锁相环中，其中电容器可被分配不同的权重和/或冗余值来调谐输出频率信号。 在一个实施例中，与已经提出的其他电路相比，更精确地执行粗调和超前滞后检测，以允许变容二极管的尺寸显着降低。

公开(公告)号：US06876266B2

公开(公告)日：2005-04-05

申请号：US10443835

申请日：2003-05-23

申请人： Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03B5/08 ,  H03B1/00 ,  H03B5/12 ,  H03L7/099 ,  H03B5/00

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

摘要： A voltage-controlled oscillator including an active oscillator circuit, an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator. Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit. To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors. The resistors can be configured in several different ways so that the voltage-controlled oscillator can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

摘要翻译： 公开了一种包括有源振荡器电路，电感器和电容电路的压控振荡器。 电容电路选择性地导通和截止以控制压控振荡器的频率。 特别地，电容电路中的电感器和电容器形成LC电路，向有源振荡器电路提供反馈。 为了避免损坏电容电路中的开关，电容电路还包括电阻器。 电阻器可以以几种不同的方式配置，使得压控振荡器可以具有高可靠性，以及具有恒定相位噪声性能的宽调谐范围。

公开(公告)号：US07945208B2

公开(公告)日：2011-05-17

申请号：US11889355

申请日：2007-08-10

申请人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong Woo Lee

发明人： Joonbae Park ,  Kyeongho Lee ,  Yido Koo ,  Jeong Woo Lee

IPC分类号： H04W88/02

CPC分类号： H04B1/1607

摘要： Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.

摘要翻译： RFIC的实施例和用于相同和移动终端的方法可以在内部减小输入电压以向射频收发器提供规定的电压。 RFIC的实施例可以具有高效率和/或低噪声。 在一个实施例中，设备可以包括PMIC和RFIC。 RFIC可以包括用于执行RF传输和RF接收的RF收发器，用于降低由PMIC提供的电压的DC-DC转换器和LDO调节器，以将降低的电压调节到由RF收发器使用的固定电压 。

公开(公告)号：US07768097B2

公开(公告)日：2010-08-03

申请号：US10927012

申请日：2004-08-27

申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H01L23/58 ,  H01L29/00 ,  H03B7/06

CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线 到包的第二个I / O引脚。 为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。 第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。 在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

公开(公告)号：US20050045986A1

公开(公告)日：2005-03-03

申请号：US10927012

申请日：2004-08-27

申请人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H01L20060101 ,  H01L23/64 ,  H01L29/00

CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线 到包的第二个I / O引脚。 为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。 第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。 在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

公开(公告)号：US06850748B2

公开(公告)日：2005-02-01

申请号：US10207986

申请日：2002-07-31

申请人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Eunseok Song ,  Seung-Wook Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H04B1/28 ,  H04B1/52 ,  H04B1/00

CPC分类号： H04B1/28 ,  H04B1/525

摘要： A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider that divides an input signal frequency by a predetermined value to produce an output signal frequency; and a frequency mixer that mixes the output signal frequency with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency and the carrier signal frequency. The predetermined value and the input signal frequency are selected such that the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency. The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

摘要翻译： 公开了一种在射频前端提供频率转换的方法和装置，包括将输入信号频率除以预定值以产生输出信号频率的分频器; 以及混频器，其将输出信号频率与载波信号频率进行混合，以产生基本上等于输出信号频率和载波信号频率之差的转换信号频率。 选择预定值和输入信号频率使得载波信号频率基本上不等于输出信号频率的整数倍。 该方法和装置可用于包括无线通信系统和无线LAN系统的无线通信接收机。

公开(公告)号：US06963620B2

公开(公告)日：2005-11-08

申请号：US10284342

申请日：2002-10-31

申请人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03C3/09 ,  H04L27/04 ,  H03D3/24 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03C3/0966 ,  H03C3/0933

摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

摘要翻译： 平移环路发射器使用至多一个锁相环（PLL）电路产生RF信号。 在一个实施例中，单个PLL产生两个本地振荡信号。 第一振荡信号与基带信号混合以产生中频信号。 第二振荡信号被输入到平移回路中，以将压控振荡器调整到期望的载波频率。 为了执行这种类型的调制，本地振荡信号的频率被设置为使得它们相对于载波频率彼此谐波相关。 其他实施例仅产生一个振荡信号。 在这些条件下，使用振荡信号产生中频信号，并且使用平移环路中的分频器产生用于将压控振荡器调节到载波频率的控制信号。 在其他实施例中，产生发射机信号而不使用任何锁相环电路。 这是通过使用晶体振荡器产生中频信号，然后在反馈环路中使用分频器来产生用于将压控振荡器调节到载波频率的控制信号来实现的。 通过最小化发射机中的锁相环电路的数量，移动手机的尺寸，成本和功率要求可能会大大降低。