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    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
    11.
    发明申请
    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application 审中-公开
    集成电路，含有1T-1C的嵌入式存储单元以及用于嵌入式存储器应用的1T-1C存储单元的制造方法

    公开(公告)号：US20100155801A1

    公开(公告)日：2010-06-24

    申请号：US12317507

    申请日：2008-12-22

    申请人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    发明人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    摘要翻译： 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）和至少部分地嵌入在半导体衬底内的电容器（130），使得电容器完全在导电层的下面。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以用作包括半导体衬底的1T-1C嵌入式存储单元，半导体衬底上的电绝缘堆叠（160），包括源极/漏极区域（142）的晶体管（140） ）和在半导体衬底上方的栅极区（141），延伸穿过电绝缘层并进入半导体衬底的沟槽（111），位于沟槽内的第一电绝缘层（131）和电容器 位于第一电绝缘层的沟槽内部。

    PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE
    12.
    发明申请
    PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE 有权
    在缓存行上执行多位错误校正

    公开(公告)号：US20100146368A1

    公开(公告)日：2010-06-10

    申请号：US12331255

    申请日：2008-12-09

    申请人： Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

    发明人： Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/2921 ,  G06F11/1064 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/2918

    摘要： A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

    摘要翻译： 处理器可以包括高速缓存，其可以在处理器以低功率模式操作时被分成第一和第二部分。 第一部分的高速缓存行可以被分段成段。 第一编码器可以在对数据流的第一部分进行编码的同时产生第一数据位和校验位，并且第二编码器可以分别在编码数据流的第二部分时生成第二数据位和校验位。 第一数据位可以存储在第一部分的第一部分中，并且与第一部分相关联的第二部分的第一部分中的校验位。 第一解码器可以使用存储在第一部分中的校验位来校正第一数据位中的多位位置中的错误，并且第二解码器可以单独地使用第二组校验位对第二数据位进行解码。

    Increasing the surface area of a memory cell capacitor
    13.
    发明申请
    Increasing the surface area of a memory cell capacitor 有权
    增加存储单元电容器的表面积

    公开(公告)号：US20080237796A1

    公开(公告)日：2008-10-02

    申请号：US11731193

    申请日：2007-03-30

    申请人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    发明人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

    摘要翻译： 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 在第三绝缘层上沉积第二导电层。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

    Dual gate oxide one time programmable (OTP) antifuse cell
    15.
    发明授权
    Dual gate oxide one time programmable (OTP) antifuse cell 有权
    双栅氧化层一次可编程（OTP）反熔丝

    公开(公告)号：US07280425B2

    公开(公告)日：2007-10-09

    申请号：US11239903

    申请日：2005-09-30

    申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

    摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

    摘要翻译： 一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物 存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

    Purge-based floating body memory
    16.
    发明授权
    Purge-based floating body memory 有权
    基于清洗的浮体记忆

    公开(公告)号：US07230846B2

    公开(公告)日：2007-06-12

    申请号：US11151982

    申请日：2005-06-14

    申请人： Ali Keshavarzi ,  Stephen H Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M Khellah ,  Yibin Ye ,  Vivek K De ,  Gerhard Schrom

    发明人： Ali Keshavarzi ,  Stephen H Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M Khellah ,  Yibin Ye ,  Vivek K De ,  Gerhard Schrom

    IPC分类号： G11C11/34

    CPC分类号： G11C11/404 ,  G11C2211/4016

    摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

    摘要翻译： 通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。 每个存储单元包括具有能够存储电荷的浮动体的晶体管。 多个字线和清除线与存储器单元的行互连。 多个位线被连接到存储器单元的列。 通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

    Dual gate oxide one time programmable (OTP) antifuse cell
    17.
    发明申请
    Dual gate oxide one time programmable (OTP) antifuse cell 有权
    双栅氧化层一次可编程（OTP）反熔丝

    公开(公告)号：US20070076463A1

    公开(公告)日：2007-04-05

    申请号：US11239903

    申请日：2005-09-30

    申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

    发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C17/146 ,  G11C17/165 ,  G11C29/027

    摘要： According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

    摘要翻译： 根据本发明的实施例，一次可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。 在实施例中，存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则跨越存取晶体管的栅极/漏极结的电压不足以导致 栅极氧化层的存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

    Memory cell driver circuits
    18.
    发明申请
    Memory cell driver circuits 有权
    存储单元驱动电路

    公开(公告)号：US20060291265A1

    公开(公告)日：2006-12-28

    申请号：US11169106

    申请日：2005-06-27

    申请人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    发明人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad Khellah ,  Vivek De

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18

    摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

    摘要翻译： 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

    OTP antifuse cell and cell array
    20.
    发明授权
    OTP antifuse cell and cell array 有权
    OTP反熔丝电池和电池阵列

    公开(公告)号：US07102951B2

    公开(公告)日：2006-09-05

    申请号：US10979605

    申请日：2004-11-01

    申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De

    IPC分类号： G11C17/18

    CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

    摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

    摘要翻译： 包括一次性可编程反熔丝电池的不同实施例。 在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。 反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。 感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。 高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。