Apparatus and related method for generating output clock
    11.
    发明授权
    Apparatus and related method for generating output clock 有权
    用于产生输出时钟的装置和相关方法

    公开(公告)号:US07663416B2

    公开(公告)日:2010-02-16

    申请号:US11847343

    申请日:2007-08-30

    Abstract: An apparatus for generating an audio output clock is disclosed. The apparatus at least includes a plurality of dividers and a frequency synthesizer. The apparatus utilizes the dividers to achieve dispersive frequency-division operations such that the anti-noise ability of the apparatus can be improved. In addition, the apparatus also utilizes dynamic phase adjustment to increase accuracy of the frequency of the audio output clock.

    Abstract translation: 公开了一种用于产生音频输出时钟的装置。 该装置至少包括多个分频器和频率合成器。 该装置利用分频器实现色散分频操作,从而可以提高装置的抗噪声能力。 此外,该装置还利用动态相位调整来提高音频输出时钟频率的精度。

    Phase frequency detector used in digital PLL system
    13.
    发明授权
    Phase frequency detector used in digital PLL system 有权
    数字PLL系统中使用的相位频率检测器

    公开(公告)号:US07382163B2

    公开(公告)日:2008-06-03

    申请号:US10820473

    申请日:2004-04-07

    CPC classification number: H03D13/004

    Abstract: A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the second input signal; and a reset unit outputting a first reset signal to reset the phase error detector, and outputting a second reset signal to reset the phase error judgment unit, according to the phase error judgment signal.

    Abstract translation: 相位频率检测器包括:相位误差检测器,输出根据第一输入信号和第二输入信号的相位误差信号; 相位误差判断单元,根据第一输入信号和第二输入信号输出相位误差判定信号; 以及复位单元,输出第一复位信号以复位相位误差检测器,并且根据相位误差判断信号输出第二复位信号以复位相位误差判断单元。

    Chip with adjustable pinout function and method thereof
    14.
    发明授权
    Chip with adjustable pinout function and method thereof 有权
    具有可调引脚排列功能的芯片及其方法

    公开(公告)号:US07372298B2

    公开(公告)日:2008-05-13

    申请号:US11277361

    申请日:2006-03-24

    CPC classification number: G06F1/22 H03K19/1732

    Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

    Abstract translation: 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚,第二引脚,逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路,第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口,并且控制第二引脚分布以耦合到第一端口或 第二个港口。

    METHOD FOR CONTROLLING DISPLAY DEVICE
    15.
    发明申请
    METHOD FOR CONTROLLING DISPLAY DEVICE 有权
    用于控制显示装置的方法

    公开(公告)号:US20080106641A1

    公开(公告)日:2008-05-08

    申请号:US11936058

    申请日:2007-11-06

    Applicant: Yu-Pin Chou

    Inventor: Yu-Pin Chou

    Abstract: A method for controlling a display device is disclosed. The method includes receiving an input video image having a plurality of active scan lines, controlling the display device to display a plurality of background scan lines on a first display area with a first scan line frequency, and controlling the display device to display an output image on a second display area with a second scan line frequency. A second aspect ratio of the output image is substantially equal to a first aspect ratio of the input video image. The second scan line frequency is substantially lower than the first scan line frequency.

    Abstract translation: 公开了一种用于控制显示装置的方法。 该方法包括:接收具有多条主动扫描线的输入视频图像,控制显示装置在具有第一扫描线频率的第一显示区域上显示多条背景扫描线,并且控制显示装置显示输出图像 在具有第二扫描线频率的第二显示区域上。 输出图像的第二宽高比基本上等于输入视频图像的第一宽高比。 第二扫描线频率基本上低于第一扫描线频率。

    FRAME SYNCHRONIZATION METHOD AND DEVICE UTILIZING FRAME BUFFER
    16.
    发明申请
    FRAME SYNCHRONIZATION METHOD AND DEVICE UTILIZING FRAME BUFFER 有权
    框架同步方法和使用框架缓冲器的设备

    公开(公告)号:US20080062185A1

    公开(公告)日:2008-03-13

    申请号:US11531281

    申请日:2006-09-13

    CPC classification number: G09G5/37 G06F3/14 G09G5/12 G09G2340/0435 G09G2340/10

    Abstract: A frame synchronization method includes: temporarily storing input data of at least one source frame in a frame buffer according to an input time sequence; generating an output time sequence according to the input time sequence and a delay time; generating output data of a destination frame according to the input data of the source frame; and outputting the output data of the destination frame according to an output time sequence; wherein an average frame rate of the source frame is substantially the same as that of the destination frame.

    Abstract translation: 帧同步方法包括:根据输入的时间序列临时存储帧缓冲器中的至少一个源帧的输入数据; 根据输入时间序列和延迟时间生成输出时间序列; 根据源帧的输入数据生成目的地帧的输出数据; 并根据输出时间序列输出目的地帧的输出数据; 其中所述源帧的平均帧速率与所述目的地帧的平均帧速率基本相同。

    Sync signal acquisition device
    17.
    发明申请
    Sync signal acquisition device 有权
    同步信号采集装置

    公开(公告)号:US20080007656A1

    公开(公告)日:2008-01-10

    申请号:US11822392

    申请日:2007-07-05

    CPC classification number: H04N5/08 H04N5/185 H04N9/44

    Abstract: A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

    Abstract translation: 公开了一种同步信号采集装置,其包括晶体管,电阻器,钳位器,模拟多路复用器和比较器。 当在复合HS模式下操作时,在产生同步信号HS之前,本发明使用常规电路在启动时提取复合同步信号,从而允许相关电路产生同步信号HS和钳位信号。 然后,使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。 此时,阻尼器的输出电压由使用者而不是过程设定; 因此,直流电压电平更可控,但由于过程变化或温度变化而不会发生漂移。

    Method for controlling display device
    19.
    发明授权
    Method for controlling display device 有权
    控制显示装置的方法

    公开(公告)号:US08471958B2

    公开(公告)日:2013-06-25

    申请号:US11936058

    申请日:2007-11-06

    Applicant: Yu-Pin Chou

    Inventor: Yu-Pin Chou

    Abstract: A method for controlling a display device is disclosed. The method includes receiving an input video image having a plurality of active scan lines, controlling the display device to display a plurality of background scan lines on a first display area with a first scan line frequency, and controlling the display device to display an output image on a second display area with a second scan line frequency. A second aspect ratio of the output image is substantially equal to a first aspect ratio of the input video image. The second scan line frequency is substantially lower than the first scan line frequency.

    Abstract translation: 公开了一种用于控制显示装置的方法。 该方法包括:接收具有多条主动扫描线的输入视频图像,控制显示装置在具有第一扫描线频率的第一显示区域上显示多条背景扫描线,并且控制显示装置显示输出图像 在具有第二扫描线频率的第二显示区域上。 输出图像的第二宽高比基本上等于输入视频图像的第一宽高比。 第二扫描线频率基本上低于第一扫描线频率。

    Power-on reset circuit
    20.
    发明授权
    Power-on reset circuit 有权
    上电复位电路

    公开(公告)号:US08446189B2

    公开(公告)日:2013-05-21

    申请号:US12794227

    申请日:2010-06-04

    CPC classification number: H03K17/20

    Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

    Abstract translation: 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号,并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号,耦合到钳位信号发生器用于从其接收钳位信号,并且可操作以根据触发信号和钳位信号产生复位信号。

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