公开(公告)号：US20050095783A1

公开(公告)日：2005-05-05

申请号：US10702711

申请日：2003-11-05

申请人： Barbara Haselden ,  John Lee

发明人： Barbara Haselden ,  John Lee

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/336

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/28273 ,  H01L21/32137

摘要： A method of forming a double gate structure including sidewalls of substantially similar vertical profile. One photoresist masking step is used to define the top gate, which is then used as a mask to define the bottom gate. The bottom polysilicon layer is etched by a physical and chemical process combination to form a bottom gate with vertical sidewalls substantially inline with the sidewalls of the top gate.

摘要翻译： 一种形成双栅极结构的方法，该双栅极结构包括基本相似的垂直剖面的侧壁。 一个光致抗蚀剂掩模步骤用于限定顶部栅极，然后将其用作掩模以限定底部栅极。 通过物理和化学处理组合来蚀刻底部多晶硅层以形成具有与顶部栅极的侧壁基本一致的垂直侧壁的底部栅极。

公开(公告)号：US07355239B1

公开(公告)日：2008-04-08

申请号：US11514743

申请日：2006-08-31

申请人： Barbara Haselden ,  Yi Ding

发明人： Barbara Haselden ,  Yi Ding

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/76224 ,  H01L27/11521 ,  Y02P80/30

摘要： Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.

摘要翻译： 提供制造半导体器件的改进方法以减少器件隔离沟槽中的介电损耗。 在一个示例中，制造半导体器件的方法包括在衬底中形成多个浅沟槽隔离（STI）沟槽。 在衬底上形成隧道氧化物层，第一导电层，栅极介电层和第二导电层。 蚀刻这些层以描绘多个堆叠的栅极结构。 特别地，蚀刻可以包括：执行第二导电层的第一蚀刻，其中STI沟槽上方的第二导电层的至少一部分保持跟随第一蚀刻; 以及执行所述第二导电层的第二蚀刻，其中所述STI沟槽上方的所述第二导电层的剩余部分和所述STI沟槽上方的所述栅极电介质层的部分通过所述第二蚀刻被完全去除。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

公开(公告)号：US20050170578A1

公开(公告)日：2005-08-04

申请号：US10772520

申请日：2004-02-04

申请人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

发明人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11539 ,  H01L27/115 ,  H01L27/11526

摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

摘要翻译： 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。

公开(公告)号：US06566196B1

公开(公告)日：2003-05-20

申请号：US10146979

申请日：2002-05-15

申请人： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

发明人： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  Y10S438/954

摘要： In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.

摘要翻译： 在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。 在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。 该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。 因此，可以用各向同性蚀刻去除氮化硅。 因此，减小了对衬底隔离电介质（210）的潜在损害。 还提供了其他实施例。

公开(公告)号：US6121154A

公开(公告)日：2000-09-19

申请号：US997346

申请日：1997-12-23

申请人： Barbara Haselden ,  John Lee ,  Chau Arima ,  Eddie Chiu

发明人： Barbara Haselden ,  John Lee ,  Chau Arima ,  Eddie Chiu

IPC分类号： G03F7/40 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01L21/31116 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/31144

摘要： A method for improving profile control during an etch of a nitride layer disposed above a silicon substrate is disclosed. The nitride layer 106 is disposed below a photoresist mask 108A. The method includes positioning the substrate, including the nitride layer and the photoresist mask, in a plasma processing chamber. There is also included flowing a chlorine-containing etchant source gas into the plasma processing chamber. Further, there is included igniting a plasma out of the chlorine-containing etchant source gas to form a chlorine-based plasma within the plasma processing chamber. Additionally, there is included treating, using a chlorine-based plasma, the photoresist mask in the plasma processing chamber. The treatment of the photoresist is configured to etch at least a portion of the photoresist mask and to deposit passivation polymer on vertical sidewalls of the photoresist mask without etching through the nitride layer.

摘要翻译： 公开了一种在硅衬底上设置的氮化物层的蚀刻期间改进形状控制的方法。 氮化物层106设置在光致抗蚀剂掩模108A的下方。 该方法包括将包括氮化物层和光致抗蚀剂掩模的衬底定位在等离子体处理室中。 还包括将含氯蚀刻剂源气体流入等离子体处理室。 此外，包括从含氯蚀刻剂源气体点燃等离子体，以在等离子体处理室内形成氯基等离子体。 此外，包括使用氯基等离子体处理等离子体处理室中的光致抗蚀剂掩模。 光致抗蚀剂的处理被配置为蚀刻光致抗蚀剂掩模的至少一部分并且将钝化聚合物沉积在光致抗蚀剂掩模的垂直侧壁上，而不通过氮化物层进行蚀刻。