公开(公告)号：US12119814B2

公开(公告)日：2024-10-15

申请号：US18183806

申请日：2023-03-14

Applicant: pSemi Corporation

Inventor： Ravindranath D. Shrivastava ,  Alper Genc

IPC: H03K17/16 ,  H03K17/041 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/687 ,  H03K17/693 ,  H04B1/44 ,  H01L27/06

CPC classification number: H03K17/687 ,  H03K17/063 ,  H01L27/0629

Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.

公开(公告)号：US10797172B2

公开(公告)日：2020-10-06

申请号：US16046974

申请日：2018-07-26

Applicant: pSemi Corporation

Inventor： Christopher N. Brindle ,  Jie Deng ,  Alper Genc ,  Chieh-Kai Yang ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Mark L. Burgener ,  Robert B. Welstand

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/49 ,  H01L29/786 ,  H03K17/16 ,  H01L49/02 ,  H01L29/08 ,  H01L29/10

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

公开(公告)号：US20190237579A1

公开(公告)日：2019-08-01

申请号：US16377026

申请日：2019-04-05

Applicant: pSemi Corporation

Inventor： Christopher N. Brindle ,  Jie Deng ,  Alper Genc ,  Chieh-Kai Yang

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H03K17/16 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L49/02 ,  H01L29/10 ,  H01L29/08

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

公开(公告)号：US11923838B2

公开(公告)日：2024-03-05

申请号：US17807663

申请日：2022-06-17

Applicant: pSemi Corporation

Inventor： Alper Genc ,  Peter Bacon

IPC: H03K17/687 ,  H03K17/06 ,  H03K17/10

CPC classification number: H03K17/687 ,  H03K17/06 ,  H03K17/102 ,  H03K2017/066

Abstract: Methods and devices to reduce the gate-induced drain/body leakage current (GIDL) generated in FET switch stacks when in OFF state are disclosed. Such devices include inductors as part of bias networks coupled with drain/source terminals and/or body terminals of the transistors within the switch stack. Hybrid approaches where resistors in combination with inductors are implemented as part the bias network are also described.

公开(公告)号：US11671090B2

公开(公告)日：2023-06-06

申请号：US17386409

申请日：2021-07-27

Applicant: pSemi Corporation

Inventor： Alper Genc

IPC: H03K17/16 ,  H03K17/693

CPC classification number: H03K17/162 ,  H03K17/693 ,  H03K2217/0018

Abstract: Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

公开(公告)号：US11463087B2

公开(公告)日：2022-10-04

申请号：US16945283

申请日：2020-07-31

Applicant: pSemi Corporation

Inventor： Alper Genc

IPC: H03K17/693 ,  H03K17/76

Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.

公开(公告)号：US20200321467A1

公开(公告)日：2020-10-08

申请号：US16739093

申请日：2020-01-09

Applicant: pSemi Corporation

Inventor： Christopher N. Brindle ,  Jie Deng ,  Alper Genc ,  Chieh-Kai Yang

IPC: H01L29/78 ,  H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H03K17/16 ,  H01L29/10 ,  H01L29/36 ,  H01L29/49 ,  H01L29/786

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.