摘要:
A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
摘要:
A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
摘要:
A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.
摘要:
An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.
摘要:
A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.
摘要:
A system and method for adjusting the perceived depth of stereoscopic images are provided. The system includes a disparity estimator, a disparity processor and a warping engine. The disparity estimator is configured to receive a stereoscopic image, to estimate disparities in the stereoscopic image, and to generate an estimator signal comprising the estimated disparities. The disparity processor is configured to receive the estimator signal from the disparity estimator and a depth control signal that is generated based on a user input. The disparity processor is also configured to generate a processor signal based on the estimator signal and the depth control signal. The warping engine is configured to receive the processor signal and to generate an adjusted stereoscopic image by warping the processor signal based on a model.
摘要:
An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.
摘要:
A receive channel offset correction scheme utilizes “eye edge” samplers and demultiplexers already present and essential for operation of the CDR algorithm, and adds only simple word-rate logic, with no new analog circuitry. The result is the ability to precisely determine the offset polarity as well as to get an approximate immediate measure of the offset magnitude. The offset detected includes all of the analog circuitry in the channel, including the samplers themselves.
摘要:
A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.
摘要:
A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.