公开(公告)号：US07946498B2

公开(公告)日：2011-05-24

申请号：US11468061

申请日：2006-08-29

Applicant: Hui-Chen Chiu

Inventor： Hui-Chen Chiu

IPC: G06K19/06 ,  G06K19/00

CPC classification number: G06K19/07 ,  G06K19/07703

Abstract: A memory module with display functions and a display unit thereof are provided. The memory module includes a first circuit board, a memory chip, a display unit and a controller. The memory chip is disposed on the first circuit board. The display unit is disposed on the first circuit board. The display unit has the same package type as the memory chip. The controller is disposed on the first circuit board. The controller is configured to control the memory chip and provide information about the memory chip to the display unit, such that the display unit is capable of displaying information about the memory chip.

Abstract translation: 提供具有显示功能的存储模块及其显示单元。 存储器模块包括第一电路板，存储器芯片，显示单元和控制器。 存储芯片设置在第一电路板上。 显示单元设置在第一电路板上。 显示单元具有与存储芯片相同的封装类型。 控制器设置在第一电路板上。 控制器被配置为控制存储器芯片并且向显示单元提供关于存储器芯片的信息，使得显示单元能够显示关于存储器芯片的信息。

公开(公告)号：US07937522B2

公开(公告)日：2011-05-03

申请号：US11699372

申请日：2007-01-30

Applicant: Chun-Kun Lee ,  Wei-Yi Hsiao

Inventor： Chun-Kun Lee ,  Wei-Yi Hsiao

IPC: G06F13/00

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The method for managing flash memory data includes the following steps. When data are first transmitted from a host and the address for the data indicates a temporary address, then temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash buffer. When the buffer of the flash memory is not full, the buffer data are written into a temporary block. The method of writing the buffer data into the temporary block includes using a address changing command, or executing a writing command to rewrite the external buffer data to the flash buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的方法包括以下步骤。 当首先从主机发送数据，并且数据的地址指示临时地址时，将临时数据从临时地址检索到外部缓冲器。 然后执行写命令，并将具有目的地址的临时数据写入闪存缓冲器。 当闪速存储器的缓冲区不满时，缓冲区数据被写入临时块。 将缓冲器数据写入临时块的方法包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪速缓冲器，使得数据被写入临时块。

公开(公告)号：US07760564B2

公开(公告)日：2010-07-20

申请号：US12379202

申请日：2009-02-17

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: G11C11/00

CPC classification number: G11C29/832 ,  G11C29/006 ,  G11C29/78

Abstract: A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number.

Abstract translation: 非易失性存储器阵列结构包括N位线，M个第一字线，M×N个第一存储器单元，第二字线，n个修复电路和读出放大器。 N位线和M个第一字线被隔行扫描以控制M×N个第一存储单元。 第二个字线被放置在n个位线之间。 每个修复电路电连接在相应的位线和读出放大器之间。 M和N是自然数。

公开(公告)号：US07653067B2

公开(公告)日：2010-01-26

申请号：US11561787

申请日：2006-11-20

Applicant: Shin-Ping Lin ,  Chun-Ching Huang

Inventor： Shin-Ping Lin ,  Chun-Ching Huang

IPC: H04L12/56 ,  G06F7/00

CPC classification number: G11B27/3027 ,  G11B27/105 ,  H04M1/72558

Abstract: A block-based seeking method for Windows Media Audio (WMA) stream can be implemented in a portable electronic device with a first processor and a second processor. The first processor initially reads a WMA stream from a block-based storage device. Next, the WMA stream is transmitted to a memory of a second processor block by block. The first processor generates and transmits a block number before it transmits a block of data. Next, the second processor decodes the WMA stream packet by packet. If a discontinuous block number occurs, a desired position of the WMA stream is sought according to the discontinuous block number. Next, the second processor outputs decoded samples of the WMA stream.

Abstract translation: 用于Windows Media Audio（WMA）流的基于块的搜索方法可以在具有第一处理器和第二处理器的便携式电子设备中实现。 第一处理器最初从基于块的存储设备读取WMA流。 接下来，WMA流被逐个传送到第二处理器的存储器。 第一处理器在发送数据块之前产生并发送块号。 接下来，第二处理器通过分组解码WMA流分组。 如果发生不连续块号，则根据不连续块号寻求WMA流的期望位置。 接下来，第二处理器输出WMA流的解码样本。

公开(公告)号：US20070169086A1

公开(公告)日：2007-07-19

申请号：US11320600

申请日：2005-12-30

Applicant: Chin-Wei Cheng ,  Wen-Chung Chang

Inventor： Chin-Wei Cheng ,  Wen-Chung Chang

IPC: G06F9/44

CPC classification number: G06F8/65

Abstract: A system for updating In-System Program (ISP) comprises an ISP loader that is called when an Interrupt Function Table is matched, an ISP RAM space has run out, or a page fault has happened. When an Interrupt Function Table is matched, a Function is partially updated; when an ISP RAM space has run out, a Function is executed; and when a page fault has happened, the page fault address is recorded and the page fault is corrected.

Abstract translation: 用于更新系统内程序（ISP）的系统包括当中断功能表匹配时ISP调用的ISP加载程序，ISP的RAM空间已经用完或页面错误发生。 当中断功能表匹配时，功能部分更新; 当ISP RAM空间已经用尽时，执行一个功能; 并且当发生页错误时，记录页错误地址，并更正页错误。

公开(公告)号：US09405485B2

公开(公告)日：2016-08-02

申请号：US14319990

申请日：2014-06-30

Applicant: SILICONMOTION INC.

Inventor： Chun-Kun Lee ,  Wei-Yi Hsiao

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到 外部缓冲区 然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。 当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。 将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。

公开(公告)号：US20120198142A1

公开(公告)日：2012-08-02

申请号：US13443342

申请日：2012-04-10

Applicant: Chun-Kun Lee ,  Wei-Yi Hsiao

Inventor： Chun-Kun Lee ,  Wei-Yi Hsiao

IPC: G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0646 ,  G06F12/0802 ,  G06F13/1673 ,  G06F2212/7203

Abstract: The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Abstract translation: 用于管理闪存数据的系统和装置包括主机发送数据，其中当从主机发送的数据具有第一时间传输特性并且数据的地址指示临时地址时，将临时数据从临时地址检索到 外部缓冲区 然后执行写入命令，并且具有目的地地址的临时数据被写入闪存缓冲器。 当闪存缓冲器未满时，缓冲器数据被写入闪速存储器的临时块。 将缓冲器数据写入临时块包括使用地址改变命令，或执行写入命令将外部缓冲器数据重写到闪存缓冲器，使得数据被写入临时块。

公开(公告)号：US07377432B2

公开(公告)日：2008-05-27

申请号：US11436576

申请日：2006-05-19

Applicant: Wallace Kou ,  Chang-Lung Lu ,  Sheng-I Hsu

Inventor： Wallace Kou ,  Chang-Lung Lu ,  Sheng-I Hsu

IPC: G06K7/06

CPC classification number: G06F13/4045

Abstract: An interface converting apparatus that converts signals between a Secure Digital (SD) card and a Memory Stick Pro (MS Pro). The apparatus comprises a SD memory card interface, a MS Pro memory card interface, an address decoder and a micro controller. The micro controller is able to convert a memory address from the MS Pro memory card interface into a memory address needed by the SD memory card interface and vice versa, and the address decoder can then be used to access the data via the SD memory card interface or the MS Pro memory card interface.

Abstract translation: 一种在安全数字（SD）卡和记忆棒Pro（MS Pro）之间转换信号的接口转换装置。 该装置包括SD存储卡接口，MS Pro存储卡接口，地址解码器和微控制器。 微控制器能够将存储器地址从MS Pro存储卡接口转换为SD存储卡接口所需的存储器地址，反之亦然，然后地址解码器可用于通过SD存储卡接口访问数据 或MS Pro存储卡接口。

公开(公告)号：US20080012149A1

公开(公告)日：2008-01-17

申请号：US11487304

申请日：2006-07-17

Applicant: Te-Wei Chen

Inventor： Te-Wei Chen

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor chip structure includes a top metal layer and an inter-layer dielectric under the top metal layer. The top metal layer includes a bonding pad area and a non-bonding pad area. The inter-layer dielectric includes at least one first via disposed under the bonding pad area, and a plurality of conventional second vias disposed under the non-bonding pad area. The size of the first via is much larger than the size of the second via to improve bonding pad reliability. The cross section of the first via is a rectangular, a square, or a polygonal. The top metal layer has a predefined thickness to improve a yield of a wire bonding.

Abstract translation: 半导体芯片结构包括在顶部金属层下方的顶部金属层和层间电介质。 顶部金属层包括焊盘区域和非接合焊盘区域。 层间电介质包括设置在焊盘区域下方的至少一个第一通孔和设置在非接合焊盘区域下方的多个传统的第二通孔。 第一通孔的尺寸比第二通孔的尺寸大得多，以提高焊盘的可靠性。 第一通孔的横截面是矩形，正方形或多边形。 顶部金属层具有预定的厚度以提高引线接合的产量。

公开(公告)号：US20070285362A1

公开(公告)日：2007-12-13

申请号：US11468061

申请日：2006-08-29

Applicant: Hui-Chen Chiu

Inventor： Hui-Chen Chiu

IPC: G09G3/36

CPC classification number: G06K19/07 ,  G06K19/07703

Abstract: A memory module with display functions and a display unit thereof are provided. The memory module includes a first circuit board, a memory chip, a display unit and a controller. The memory chip is disposed on the first circuit board. The display unit is disposed on the first circuit board. The display unit has the same package type as the memory chip. The controller is disposed on the first circuit board. The controller is configured to control the memory chip and provide information about the memory chip to the display unit, such that the display unit is capable of displaying information about the memory chip.

Abstract translation: 提供具有显示功能的存储模块及其显示单元。 存储器模块包括第一电路板，存储器芯片，显示单元和控制器。 存储芯片设置在第一电路板上。 显示单元设置在第一电路板上。 显示单元具有与存储芯片相同的封装类型。 控制器设置在第一电路板上。 控制器被配置为控制存储器芯片并且向显示单元提供关于存储器芯片的信息，使得显示单元能够显示关于存储器芯片的信息。