SWITCHING-BASED CONTROL FOR A POWER CONVERTER
    11.
    发明申请
    SWITCHING-BASED CONTROL FOR A POWER CONVERTER 有权
    一种功率转换器的切换控制

    公开(公告)号:US20140319838A1

    公开(公告)日:2014-10-30

    申请号:US13871309

    申请日:2013-04-26

    Abstract: A method for operating a power generation system that supplies power for application to a load is disclosed. The method may generally include receiving, at a power converter, an alternating current power generated by a generator operating at a speed that is substantially equal to its synchronous speed and converting, with the power converter, the alternating current power to an output power, wherein the power converter includes at least one switching element. In addition, the method may include receiving a control command to control a switching frequency of the at least one switching element and adjusting the switching frequency to an adjusted switching frequency that is substantially equal to a fundamental frequency of the load.

    Abstract translation: 公开了一种用于操作向负载施加电力的发电系统的方法。 该方法通常可以包括在功率转换器处接收由发电机产生的交流电力,该发电机以基本上等于其同步速度的速度运行,并且利用功率转换器将交流电力转换为输出功率,其中 功率转换器包括至少一个开关元件。 此外,该方法可以包括接收用于控制至少一个开关元件的开关频率并将开关频率调整到基本上等于负载的基频的调节开关频率的控制命令。

    Active DC bus voltage balancing circuit

    公开(公告)号:US11984829B2

    公开(公告)日:2024-05-14

    申请号:US17558866

    申请日:2021-12-22

    CPC classification number: H02P27/06 H02M7/4833 H02P2201/01 H02P2201/03

    Abstract: A system has a DC bus circuit with first and second terminals, an intermediate node, first and second capacitors, first and second depletion mode FETs, and first and second switching control circuits, where the first depletion mode FET has a drain coupled to the first bus terminal, a source, and a gate coupled to the intermediate node, the second depletion mode FET has a drain coupled to the intermediate node, a source, and a gate coupled to the second bus terminal, the first switching control circuit turns the first depletion mode FET off responsive to a first capacitor voltage of the first bus capacitor being less than or equal to a second capacitor voltage of the second bus capacitor, and the second switching control circuit turns the second depletion mode FET off responsive to the first capacitor voltage being greater than or equal to the second capacitor voltage.

    ACTIVE DC BUS VOLTAGE BALANCING CIRCUIT
    14.
    发明公开

    公开(公告)号:US20230198446A1

    公开(公告)日:2023-06-22

    申请号:US17558866

    申请日:2021-12-22

    CPC classification number: H02P27/06 H02P27/16 H02P2201/01

    Abstract: A system has a DC bus circuit with first and second terminals, an intermediate node, first and second capacitors, first and second depletion mode FETs, and first and second switching control circuits, where the first depletion mode FET has a drain coupled to the first bus terminal, a source, and a gate coupled to the intermediate node, the second depletion mode FET has a drain coupled to the intermediate node, a source, and a gate coupled to the second bus terminal, the first switching control circuit turns the first depletion mode FET off responsive to a first capacitor voltage of the first bus capacitor being less than or equal to a second capacitor voltage of the second bus capacitor, and the second switching control circuit turns the second depletion mode FET off responsive to the first capacitor voltage being greater than or equal to the second capacitor voltage.

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