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    Variable frequency system
    11.
    发明授权
    Variable frequency system 失效
    可变频率系统

    公开(公告)号：US3651414A

    公开(公告)日：1972-03-21

    申请号：US3651414D

    申请日：1970-04-30

    Applicant: LORAIN PROD CORP

    Inventor： JAMIESON ROBERT S

    IPC: G04F10/04 ,  H03K3/72 ,  H03K21/30

    CPC classification number: H03K3/72 ,  G04F10/04

    Abstract: A digital timing system of high precision and stability is provided with a selectively variable frequency and phase by employing a variable frequency dividing circuit that is responsive to a highly accurate precision crystal clock generator. The variable divider includes a fixed modulus counter which in turn triggers a variable modulus counter. High frequency precision clock pulses are fed first to the fixed counter which upon completion of its count, switches the clock pulses to the variable counter. The latter, when it completes its count, provides an output pulse that (a) constitutes one element of the system output, (b) resets the fixed counter, and (c) switches the clock pulses to the fixed counter whereby the above cycle is repeated. To vary the frequency or repetition rate of the described cycle of operation, the magnitude of the count provided by the variable counter is changed to thereby change the total interval or period of a single cycle. To control the phase of the output signal, the count of the fixed counter is changed during but one of its counts. The variable counter is formed of a pair of reversible, up-down counters each of which provides an output upon reaching the count of one when counting down. The frequency of the output is changed by controllably varying the number to which these variable reversible counters count.

    Abstract translation: 通过采用响应于高精度精密晶体时钟发生器的可变分频电路，提供了具有高精度和稳定性的数字定时系统，其具有可选择的可变频率和相位。 可变分频器包括固定模数计数器，该计数器又触发可变模数计数器。 高频精度时钟脉冲首先馈送到固定计数器，在其计数完成后，将时钟脉冲切换到可变计数器。 后者在完成计数时提供输出脉冲，其中（a）构成系统输出的一个元件，（b）复位固定计数器，（c）将时钟脉冲切换到固定计数器，由此上述周期为 重复。 为了改变所述操作周期的频率或重复率，可变计数器提供的计数值的大小被改变，从而改变单个周期的总间隔或周期。 为了控制输出信号的相位，固定计数器的计数在其计数期间改变。 可变计数器由一对可逆的向上计数器形成，每个计数器在向下计数时达到一个计数值。 通过可控地改变这些可变可逆计数器计数的数量来改变输出的频率。

    Self-Matching Pulse Generator with Adjustable Pulse Width and Pulse Frequency
    14.
    发明申请
    Self-Matching Pulse Generator with Adjustable Pulse Width and Pulse Frequency 有权
    具有可调脉冲宽度和脉冲频率的自匹配脉冲发生器

    公开(公告)号：US20120038222A1

    公开(公告)日：2012-02-16

    申请号：US12854561

    申请日：2010-08-11

    Applicant: Tammo Heeren ,  Fred Mercado

    Inventor： Tammo Heeren ,  Fred Mercado

    IPC: H03K3/64

    CPC classification number: H03K3/72

    Abstract: Pulse-generator circuits that permit independent control of pulse widths and the delays between successive pulses. In several embodiments, a pulse-generator subcircuit includes a transmission-line segment comprising first and second conductors, configured such that the first conductor is coupled to a first DC potential. The pulse-generator subcircuit further includes a terminating resistor coupled to a first end of the second conductor of the first transmission-line segment; this terminating resistor is matched to the characteristic impedance of the transmission-line segment. The pulse-generator subcircuit further includes first and second switches, controlled by first and second timing signals, respectively, and configured to selectively and independently connect respective first and second ends of the first conductor to a second DC potential. This second potential may be ground, in some embodiments, while the DC potential supplied to the pulse-generator subcircuit by the power-supply subcircuit may range from a very small voltage to voltages exceeding a kilovolt.

    Abstract translation: 脉冲发生器电路允许独立控制脉冲宽度和连续脉冲之间的延迟。 在几个实施例中，脉冲发生器分支电路包括包括第一和第二导体的传输线段，其被配置为使得第一导体耦合到第一直流电位。 脉冲发生器分支电路还包括耦合到第一传输线段的第二导体的第一端的终端电阻器; 该终端电阻与传输线段的特性阻抗匹配。 脉冲发生器分支电路还包括分别由第一和第二定时信号控制的第一和第二开关，并且被配置为选择性地且独立地将第一导体的第一和第二端连接到第二直流电位。 在一些实施例中，该第二电位可以被研磨，而由电源子电路提供给脉冲发生器子电路的DC电压可以在非常小的电压到超过千伏的电压的范围。

    Electronic circuit for producing an irregular pulse train of variable frequency and duty cycle
    15.
    发明授权
    Electronic circuit for producing an irregular pulse train of variable frequency and duty cycle 失效
    用于产生可变频率和占空比的不规则脉冲串的电子电路

    公开(公告)号：US5061905A

    公开(公告)日：1991-10-29

    申请号：US614730

    申请日：1990-11-16

    Applicant: Joseph Truchsess

    Inventor： Joseph Truchsess

    IPC: A63H19/24 ,  H03K3/0231 ,  H03K3/72

    CPC classification number: H03K3/0231 ,  A63H19/24 ,  H03K3/72

    Abstract: An inexpensive yet effective circuit for producing an irregular pulse train of variable frequency and duty cycle, particularly for generating simulated sounds, such as engine sounds for toy vehicles, is disclosed. The circuit comprises an integrated circuit including a plurality of Schmitt trigger inverters (U1A, U1B) configured for oscillation at different frequencies, and a resistance element (R3, R7) in series with one, and preferably both, of the power supply connections to the inverters, with the circuit output comprising the output of one of the Schmitt trigger inverters (U1B). In a preferred embodiment, a capacitance element (C4) is connected between the output of a Schmitt trigger inverter and its system voltage input for further modulating the circuit output.

    Abstract translation: 公开了一种用于产生可变频率和占空比的不规则脉冲串的便宜且有效的电路，特别是用于产生模拟声音，例如玩具车辆的发动机声音。 该电路包括集成电路，该集成电路包括被配置为用于不同频率振荡的多个施密特触发器逆变器（U1A，U1B），以及电阻元件（R3，R7），其与一个，优选两个电源连接 逆变器，其中电路输出包括施密特触发器（U1B）之一的输出。 在优选实施例中，电容元件（C4）连接在施密特触发逆变器的输出端与其系统电压输入端之间，用于进一步调制电路输出。

    Variable frequency logic clock
    16.
    发明授权
    Variable frequency logic clock 失效
    可变频率逻辑时钟

    公开(公告)号：US4316148A

    公开(公告)日：1982-02-16

    申请号：US71810

    申请日：1979-09-04

    Applicant: David G. Kaminski

    Inventor： David G. Kaminski

    IPC: G06F1/08 ,  H03K3/72 ,  H03K5/06 ,  H03K3/017

    CPC classification number: G06F1/08 ,  H03K3/72 ,  H03K5/06

    Abstract: A logic clock signal generator implemented with delay lines having a plurality of taps, wherein the taps are selectively feedback coupled to the input to produce a clock signal having a plurality of selectively variable time periods.

    Abstract translation: 用具有多个抽头的延迟线实现的逻辑时钟信号发生器，其中所述抽头选择性地反馈耦合到所述输入以产生具有多个选择性可变时间段的时钟信号。

    Wideband frequency multiplier particularly adapted for use in badge readers and the like
    17.
    发明授权
    Wideband frequency multiplier particularly adapted for use in badge readers and the like 失效
    特别适用于徽章阅读器等的宽带倍频器

    公开(公告)号：US4063070A

    公开(公告)日：1977-12-13

    申请号：US741254

    申请日：1976-11-12

    Applicant: Gerard Jean-Marie Delarue ,  Michel Paul Verhaeghe

    Inventor： Gerard Jean-Marie Delarue ,  Michel Paul Verhaeghe

    IPC: G11B20/14 ,  G11B27/30 ,  H03K3/72 ,  H03K3/78 ,  H03K5/00 ,  H03K5/156 ,  G06K5/00 ,  G11B5/09

    CPC classification number: G11B27/30 ,  G11B20/1403 ,  H03K3/72 ,  H03K3/78 ,  H03K5/156

    Abstract: An improved wideband frequency multiplier characterized as follows: a saw-tooth signal generator supplying a saw-tooth wave having a frequency equal to the frequency to be multiplied, the level of the voltage wave varying between a reference level and a maximum which is related to the frequency to be multiplied; storage means for storing a voltage equal to, or closely approaching the maximum voltage value of the saw-tooth wave; a voltage divider having several outputs, each of which provides an output which is a given fraction of the stored voltage; a number of comparators each of which corresponds to and is coupled to an output of the voltage divider, each comparator comparing the instantaneous value of the saw-tooth voltage with the voltage supplied by the corresponding output of the voltage divider, and supplying a first level signal when said instantaneous value is lower than the voltage supplied by said corresponding output, and a second level signal when it is higher; and logical circuits combining the signals supplied by the comparators so as to give an output signal the frequency of which is a given multiple of the frequency of the saw-tooth signal.A timing circuit for a badge reader, or the like where the data is magnetically NRZ recorded on, or in, the badge, or the like. The timing circuit employs a frequency doubler as generally described above. The timing circuit also utilizes at least one additional logic circuit. The timing circuit provides timing signals synchronized with the reading of the data from the badge or the like.

    Abstract translation: 一种改进的宽带倍频器，其特征如下：锯齿信号发生器，其提供具有等于要乘以的频率的频率的锯齿波，电压波在参考电平与最大值之间变化的电平 频率倍增; 存储装置，用于存储等于或接近锯齿波的最大电压值的电压; 具有多个输出的分压器，每个输出提供作为所存储电压的给定分数的输出; 多个比较器，每个比较器对应并耦合到分压器的输出，每个比较器比较锯齿电压的瞬时值与由分压器的相应输出端提供的电压，并提供第一级 当所述瞬时值低于由所述对应输出提供的电压时的信号，而当所述瞬时值较高时提供第二电平信号; 以及组合由比较器提供的信号的逻辑电路，以便给出其频率是锯齿信号的频率的给定倍数的输出信号。

    Independently variable on-time and off-time pulse generator circuit
    18.
    发明授权
    Independently variable on-time and off-time pulse generator circuit 失效
    独立的可变时间和时间脉冲发生器电路

    公开(公告)号：US3854103A

    公开(公告)日：1974-12-10

    申请号：US41323073

    申请日：1973-11-06

    Applicant: TAKARADA E

    Inventor： TAKARADA E

    IPC: H03K3/03 ,  H03K3/72 ,  H03B3/10 ,  H03K5/04

    CPC classification number: H03K3/72 ,  H03K3/03

    Abstract: A pulse generator for use in an EDM power supply or the like wherein the pulse-on time and pulse-off time are each adjustable, substantially independently of the other. The circuit contains a pair of relaxation oscillators, one of which is associated with the on-time and one with the off-time of the output pulse train. The timed signals produced by the oscillators are shaped by respective Schmidt triggers for controlling a flip-flop which thereby generates the output pulse train. The flip-flop outputs are fed back to the oscillator inputs so as to allow only one of such oscillators to be active at any given time thereby allowing the on-period and off-period to be each independently timed.

    Abstract translation: 用于EDM电源等的脉冲发生器，其中脉冲开启时间和脉冲关闭时间各自可调节，基本上独立于另一个。 该电路包含一对弛豫振荡器，其中之一与导通时间相关联，一个与输出脉冲串的关闭时间相关。 由振荡器产生的定时信号由相应的施密特触发器形成，用于控制触发器，从而产生输出脉冲串。 触发器输出被反馈到振荡器输入，以便允许这些振荡器中的仅一个在任何给定时间处于活动状态，从而允许导通周期和截止周期各自独立定时。

    Program-variable clock pulse generator
    19.
    发明授权
    Program-variable clock pulse generator 失效
    程序可变时钟脉冲发生器

    公开(公告)号：US3764992A

    公开(公告)日：1973-10-09

    申请号：US3764992D

    申请日：1972-02-14

    Applicant: BELL TELEPHONE LABOR INC

    Inventor： MILNE D

    IPC: G06F1/08 ,  H03K3/72 ,  G06F1/04

    CPC classification number: G06F1/08 ,  H03K3/72

    Abstract: A binary coded character is decoded to enable one of a plurality of AND gates that are respectively actuated by outputs of different monostable multivibrators, each having a different predetermined reset delay time. The selected gate output is further delayed and then utilized to retrigger the multivibrators simultaneously and to initiate the supplying of a new character for decoding. The composite outputs of the selected gates comprise a train of pulses having a recurrence rate that varies in accordance with the information content of a succession of the aforementioned binary coded characters.

    Abstract translation: 二进制编码字符被解码以使得能够分别由不同单稳态多谐振荡器的输出致动的多个与门中的一个，每个具有不同的预定复位延迟时间。 所选择的门输出进一步延迟，然后用于同时重新触发多谐振荡器，并开始提供新的字符进行解码。 所选择的门的复合输出包括具有根据上述二进制编码字符的一系列的信息内容而变化的重复率的脉冲序列。

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