公开(公告)号：US20010034597A1

公开(公告)日：2001-10-25

申请号：US09798561

申请日：2001-03-02

发明人： Gary L. Swoboda ,  Robert A. McGowan

IPC分类号： G06F009/455

CPC分类号： G01R31/31705 ,  G06F9/455 ,  G06F11/261 ,  G06F11/3466 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/364 ,  G06F11/3648 ,  G06F11/3656 ,  Y02D10/34 ,  Y02T10/82 ,  Y10S370/914

摘要： An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.

摘要翻译： 位于集成电路（14）外部的仿真控制器（12）可以被提供有指示集成电路的内部时钟的操作的定时信息，其驱动集成电路的内部数据处理活动。 响应于内部时钟的每个周期，产生相应的数字位以表示内部时钟周期，并且以与内部时钟的时钟速率不同的输出时钟速率将数字位输出到仿真控制器。

公开(公告)号：US5195088A

公开(公告)日：1993-03-16

申请号：US628799

申请日：1990-12-17

申请人： Ralph Urbansky

发明人： Ralph Urbansky

IPC分类号： H04J3/00 ,  H04J3/07 ,  H04L7/00

CPC分类号： H04J3/076 ,  Y10S370/914

摘要： A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock. In order to prevent stationary phase shifts from producing a constant frequency shift of the oscillator, the control circuit provides a PI behavior (proportionality and integration) of the frequency control signal supplied to the oscillator.

摘要翻译： 一种用于将帧结构输入信号的比特率转换为预定标称比特率的电路装置。 输入信号的数据位通过写入地址计数器（7）以这种信号的比特率写入弹性存储器（6）中，随后借助于读地址计数器（8）再次读出， 以标称比特率的容限范围内的速率。 相位比较器（16）确定这种计数器的计数之间的距离，并产生对应于这样的距离的控制误差信号。 为了最小化读出信号的抖动，控制误差信号被提供给控制电路（18），控制电路（18）控制由读取地址计数器（8）的时钟发生器（17）产生的时钟。 时钟发生器电路包括频率可控振荡器，其输出用作读时钟。 为了防止固定相移产生振荡器的恒定频移，控制电路提供提供给振荡器的频率控制信号的PI行为（比例和积分）。

公开(公告)号：US5020053A

公开(公告)日：1991-05-28

申请号：US510198

申请日：1990-04-17

申请人： Minoru Ishikawa ,  Nobuki Nakata

发明人： Minoru Ishikawa ,  Nobuki Nakata

IPC分类号： H04J3/12 ,  H04J3/06 ,  H04M7/00

CPC分类号： H04J3/062 ,  Y10S370/914

摘要： A channel access system comprises n channel parts for receiving m channels of voice signals and for outputting voice frequency data and signaling data, and a multiplexer part for receiving the voice frequency data and the signaling data of the m channel from the n channel parts and for supplying channel access signals to the n channel parts for designating a channel of the voice frequency data, where each of the n channel parts include a coder for coding a corresponding one of the voice signals into one of the voice frequency data, a decoder for decoding the channel access signals and for generating a synchronizing signal which is synchronized to a corresponding one of the channel access signals which designates its own channel, a signaling converter for converting the corresponding one of the signaling signals into a corresponding one of the signaling data, and a speed converting circuit for converting a transmission speed of the signaling data from a first transmission speed to a second transmission speed which is higher than the first transmission speed. The synchronizing signal controls a coding timing of the coder and a speed conversion timing of the speed converting circuit.

公开(公告)号：US4241443A

公开(公告)日：1980-12-23

申请号：US28824

申请日：1979-04-10

申请人： Hiroshi Sakaki ,  Sotokichi Shintani

发明人： Hiroshi Sakaki ,  Sotokichi Shintani

IPC分类号： H04J1/10 ,  H03K7/02 ,  H04J3/00 ,  H04J4/00 ,  H04J1/05

CPC分类号： H04J4/005 ,  Y10S370/914

摘要： An apparatus for reducing a sampling frequency which derives information with the bandwidth f.sub.B /N (N is an integer) having a sampling frequency of 2f.sub.B /N from an input FDM signal with a bandwidth up to f.sub.B having the sampling frequency 2f.sub.B has been found. The present apparatus comprises a pair of partial frequency reduction systems and a switch for alternately selecting the outputs of said partial frequency reduction systems to provide the output signal. Each of said partial frequency reduction systems comprises a DFT means for performing the discrete Fourier transform for every G sampling points (G is the multiple of N) to said input signal, a multiplication means for multiplying the predetermined frequency characteristics with the output of said DFT means, linear conversion means for linear conversion of the output of said multiplication means and for providing G/N number of data, and means for performing the inverse discrete Fourier transform to the output of said linear conversion means. The present invention reduces sampling frequency by performing a smaller number of multiplications than a prior art, thus, the structure of an apparatus can be simple.

摘要翻译： 已经找到了一种用于降低采样频率的装置，该采样频率从具有采样频率2fB的带宽高达fB的输入FDM信号中获得具有采样频率为2fB / N的带宽fB / N（N为整数）的信息。 本装置包括一对部分频率降低系统和用于交替选择所述部分频率降低系统的输出以提供输出信号的开关。 每个所述部分频率降低系统包括用于对于每个G个采样点（G是N的倍数）对所述输入信号执行离散付里叶变换的DFT装置，用于将预定频率特性与所述DFT的输出相乘的乘法装置 意味着用于对所述乘法装置的输出进行线性转换和用于提供G / N数量数据的线性转换装置，以及用于对所述线性转换装置的输出执行离散傅里叶逆变换的装置。 本发明通过执行比现有技术更少的乘法次数来降低采样频率，因此，装置的结构可以是简单的。

公开(公告)号：US4147894A

公开(公告)日：1979-04-03

申请号：US836666

申请日：1977-09-26

申请人： Yoshio Watanabe ,  Akio Saburi

发明人： Yoshio Watanabe ,  Akio Saburi

IPC分类号： H04J3/00 ,  H04B7/15 ,  H04B7/185 ,  H04B7/212 ,  H04J3/06 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04B7/212 ,  Y10S370/914

摘要： Like a conventional time division multiplex communication device, a device according to this invention comprises first terminals, a switching matrix, transducers or C/E buffers, control circuits, and second terminals. The first and second terminals are for low-speed and high-speed signal sequences. The control circuits are connected to the second terminals. In contrast to the conventional one, the transducers are connected to the respective first terminals, with the switching matrix interposed between the transducers and the control circuits and rendered capable of dealing with the high-speed signal sequences, among others, rather than the low-speed ones as in the conventional device. The devices are particularly useful in earth stations of TDMA satellite communication to which multi-transponder operation is applied, although useful also in carrying out conversion between low-frequency analog signal or PAM signal sequences and PAM signal sequences of a higher rate.

摘要翻译： 像传统的时分复用通信设备一样，根据本发明的设备包括第一终端，交换矩阵，换能器或C / E缓冲器，控制电路和第二终端。 第一和第二端子用于低速和高速信号序列。 控制电路连接到第二端子。 与常规的传感器相反，换能器连接到相应的第一端子，其中开关矩阵插入在换能器和控制电路之间，并且能够处理高速信号序列，而不是低频信号序列， 如常规设备那样。 这些装置在应用多应答器操作的TDMA卫星通信的地球站中特别有用，尽管在执行低频模拟信号或PAM信号序列和较高速率的PAM信号序列之间的转换方面也是有用的。

公开(公告)号：US20140044080A1

公开(公告)日：2014-02-13

申请号：US14057969

申请日：2013-10-18

申请人： Panasonic Corporation

发明人： Sadaki Futagi ,  Daichi Imamura ,  Atsushi Matsumoto ,  Takashi Iwai

IPC分类号： H04L5/00

CPC分类号： H04W52/262 ,  H04L1/0003 ,  H04L1/0004 ,  H04L1/0005 ,  H04L1/0009 ,  H04L1/001 ,  H04L1/0011 ,  H04L1/0016 ,  H04L1/0026 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/0058 ,  H04L5/006 ,  H04L27/2614 ,  H04W52/267 ,  H04W72/042 ,  H04W72/08 ,  Y10S370/914

摘要： Provided is a communication device, which is enabled to improve the throughput of a communication system by reducing the difference of a transmission power between an SCCH and an SDCH thereby to satisfy the required quality of a PAPR. In this device, an MCS selection unit (111) of a transmission unit (110) decides, with reference to a CQI lookup table, an MCS pattern (MCS1) of the SDCH, an MCS pattern (MCS2) of the SCCH and information (multiplex information) on multiplex positions on the time axes of those two channels, on the basis of the CQI information. On the basis of the MCS2 and the MCS1, encoding modulation units (112 and 113) perform encoding and modulating operations. According to the multiplex information, a channel multiplexing unit (114) time-division multiplexes the SCCH and the SDCH thereby to generate a transmission signal.

摘要翻译： 提供了一种通信装置，其能够通过减少SCCH和SDCH之间的发送功率的差异来提高通信系统的吞吐量，从而满足PAPR的所需质量。 在该装置中，发送部（110）的MCS选择部（111）参照CQI查找表，决定SDCH的MCS模式（MCS1），SCCH的MCS模式（MCS2）和信息（ 多路复用信息），根据CQI信息，对这两个信道的时间轴上的多路复用位置进行复用。 基于MCS2和MCS1，编码调制单元（112和113）进行编码和调制操作。 根据多路复用信息，信道复用单元（114）对SCCH和SDCH进行时分复用，从而生成发送信号。

公开(公告)号：US08619619B2

公开(公告)日：2013-12-31

申请号：US13789358

申请日：2013-03-07

申请人： Panasonic Corporation

发明人： Sadaki Futagi ,  Daichi Imamura ,  Atsushi Matsumoto ,  Takashi Iwai

IPC分类号： H04L12/26

CPC分类号： H04W52/262 ,  H04L1/0003 ,  H04L1/0004 ,  H04L1/0005 ,  H04L1/0009 ,  H04L1/001 ,  H04L1/0011 ,  H04L1/0016 ,  H04L1/0026 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/0058 ,  H04L5/006 ,  H04L27/2614 ,  H04W52/267 ,  H04W72/042 ,  H04W72/08 ,  Y10S370/914

摘要： Provided is a communication device, which is enabled to improve the throughput of a communication system by reducing the difference of a transmission power between an SCCH and an SDCH thereby to satisfy the required quality of a PAPR. In this device, an MCS selection unit (111) of a transmission unit (110) decides, with reference to a CQI lookup table, an MCS pattern (MCS1) of the SDCH, an MCS pattern (MCS2) of the SCCH and information (multiplex information) on multiplex positions on the time axes of those two channels, on the basis of the CQI information. On the basis of the MCS2 and the MCS1, encoding modulation units (112 and 113) perform encoding and modulating operations. According to the multiplex information, a channel multiplexing unit (114) time-division multiplexes the SCCH and the SDCH thereby to generate a transmission signal.

摘要翻译： 提供了一种通信装置，其能够通过减少SCCH和SDCH之间的发送功率的差异来提高通信系统的吞吐量，从而满足PAPR的所需质量。 在该装置中，发送部（110）的MCS选择部（111）参照CQI查找表，决定SDCH的MCS模式（MCS1），SCCH的MCS模式（MCS2）和信息（ 多路复用信息），根据CQI信息，对这两个信道的时间轴上的多路复用位置进行复用。 基于MCS2和MCS1，编码调制单元（112和113）进行编码和调制操作。 根据多路复用信息，信道复用单元（114）对SCCH和SDCH进行时分复用，从而生成发送信号。

公开(公告)号：US20130182669A1

公开(公告)日：2013-07-18

申请号：US13789358

申请日：2013-03-07

申请人： Panasonic Corporation

发明人： Sadaki Futagi ,  Daichi Imamura ,  Atsushi Matsumoto ,  Takashi Iwai

IPC分类号： H04W72/08

CPC分类号： H04W52/262 ,  H04L1/0003 ,  H04L1/0004 ,  H04L1/0005 ,  H04L1/0009 ,  H04L1/001 ,  H04L1/0011 ,  H04L1/0016 ,  H04L1/0026 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/0058 ,  H04L5/006 ,  H04L27/2614 ,  H04W52/267 ,  H04W72/042 ,  H04W72/08 ,  Y10S370/914

摘要： Provided is a communication device, which is enabled to improve the throughput of a communication system by reducing the difference of a transmission power between an SCCH and an SDCH thereby to satisfy the required quality of a PAPR. In this device, an MCS selection unit (111) of a transmission unit (110) decides, with reference to a CQI lookup table, an MCS pattern (MCS1) of the SDCH, an MCS pattern (MCS2) of the SCCH and information (multiplex information) on multiplex positions on the time axes of those two channels, on the basis of the CQI information. On the basis of the MCS2 and the MCS1, encoding modulation units (112 and 113) perform encoding and modulating operations. According to the multiplex information, a channel multiplexing unit (114) time-division multiplexes the SCCH and the SDCH thereby to generate a transmission signal.

公开(公告)号：US20120155519A1

公开(公告)日：2012-06-21

申请号：US13406374

申请日：2012-02-27

申请人： Sadaki Futagi ,  Daichi Imamura ,  Atsushi Matsumoto ,  Takashi Iwai

发明人： Sadaki Futagi ,  Daichi Imamura ,  Atsushi Matsumoto ,  Takashi Iwai

IPC分类号： H04L27/00

CPC分类号： H04W52/262 ,  H04L1/0003 ,  H04L1/0004 ,  H04L1/0005 ,  H04L1/0009 ,  H04L1/001 ,  H04L1/0011 ,  H04L1/0016 ,  H04L1/0026 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/0058 ,  H04L5/006 ,  H04L27/2614 ,  H04W52/267 ,  H04W72/042 ,  H04W72/08 ,  Y10S370/914

摘要： Provided is a communication device, which is enabled to improve the throughput of a communication system by reducing the difference of a transmission power between an SCCH and an SDCH thereby to satisfy the required quality of a PAPR. In this device, an MCS selection unit (111) of a transmission unit (110) decides, with reference to a CQI lookup table, an MCS pattern (MCS1) of the SDCH, an MCS pattern (MCS2) of the SCCH and information (multiplex information) on multiplex positions on the time axes of those two channels, on the basis of the CQI information. On the basis of the MCS2 and the MCS1, encoding modulation units (112 and 113) perform encoding and modulating operations. According to the multiplex information, a channel multiplexing unit (114) time-division multiplexes the SCCH and the SDCH thereby to generate a transmission signal.

摘要翻译： 提供了一种通信装置，其能够通过减少SCCH和SDCH之间的发送功率的差异来提高通信系统的吞吐量，从而满足PAPR的所需质量。 在该装置中，发送部（110）的MCS选择部（111）参照CQI查找表，决定SDCH的MCS模式（MCS1），SCCH的MCS模式（MCS2）和信息（ 多路复用信息），根据CQI信息，对这两个信道的时间轴上的多路复用位置进行复用。 基于MCS2和MCS1，编码调制单元（112和113）进行编码和调制操作。 根据多路复用信息，信道复用单元（114）对SCCH和SDCH进行时分复用，从而生成发送信号。

公开(公告)号：US20120058828A1

公开(公告)日：2012-03-08

申请号：US13298139

申请日：2011-11-16

申请人： James W. Morrow ,  Walter E. Eisele ,  Warren R. White

发明人： James W. Morrow ,  Walter E. Eisele ,  Warren R. White

IPC分类号： A63F9/24

CPC分类号： G07F17/323 ,  G07F17/32 ,  Y10S370/908 ,  Y10S370/911 ,  Y10S370/914

摘要： A hybrid network system and method is used for incrementally upgrading a gaming system from legacy equipment to broadband equipment while maintaining the capability to support the assets and functionality of both legacy gaming devices and networks and modern gaming devices and networks. The hybrid network system enables new gaming devices and networks to coexist in the same system as existing, legacy gaming devices and networks, and thereby upgrade components as resources and availability allow. The hybrid network system enables the addition of modern devices and networks having new capabilities while continuing to support legacy equipment that is currently in use.

摘要翻译： 混合网络系统和方法用于将游戏系统从传统设备逐渐升级到宽带设备，同时保持支持传统游戏设备和网络以及现代游戏设备和网络的资产和功能的能力。 混合网络系统使新的游戏设备和网络能够与现有的传统游戏设备和网络在同一系统中共存，从而在资源和可用性允许的情况下升级组件。 混合网络系统能够添加具有新功能的现代设备和网络，同时继续支持当前正在使用的传统设备。