公开(公告)号：US20220326304A1

公开(公告)日：2022-10-13

申请号：US17448703

申请日：2021-09-23

Applicant: DigWise Technology Corporation, LTD

Inventor： Shih-Hao CHEN ,  Chih-Wen YANG

IPC: G01R31/3193 ,  H01L21/66

Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

公开(公告)号：US20220255550A1

公开(公告)日：2022-08-11

申请号：US17590668

申请日：2022-02-01

Applicant: Rambus Inc.

Inventor： Robert E. Palmer ,  Andrew Fuller ,  Hsuan-Jung Su

IPC: H03K19/094 ,  G01R31/3193 ,  G11C11/4076 ,  G11C7/10

Abstract: An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

公开(公告)号：US11386975B2

公开(公告)日：2022-07-12

申请号：US16456094

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Joonho Song ,  Seungwon Lee

IPC: G06F11/20 ,  G06F12/0815 ,  G11C29/38 ,  H01L25/065 ,  H01L25/18 ,  G11C29/00 ,  G01R31/3193

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

公开(公告)号：US20220099729A1

公开(公告)日：2022-03-31

申请号：US17083336

申请日：2020-10-29

Applicant: SPIROX CORPORATION

Inventor： HSING-FU LIN

IPC: G01R31/28 ,  G01R31/319 ,  G01R31/3193 ,  G01R31/317

Abstract: An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

公开(公告)号：US20210389371A1

公开(公告)日：2021-12-16

申请号：US17461364

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vui Yong Liew ,  Zhenyu Zhu ,  Mikal C. Hunsaker ,  Wai Mun Ng

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F13/16 ,  G06F13/42

Abstract: An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.

公开(公告)号：US20210341547A1

公开(公告)日：2021-11-04

申请号：US16863308

申请日：2020-04-30

Applicant: SUNNY BAGGA ,  BRIAN J. CADWELL ,  SHAUN MARK GOODWIN

Inventor： SUNNY BAGGA ,  BRIAN J. CADWELL ,  SHAUN MARK GOODWIN

IPC: G01R31/52 ,  G01R31/28 ,  G01R31/3193 ,  G01R31/08 ,  G01R31/319 ,  H02H3/32 ,  H02H3/16

Abstract: A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

公开(公告)号：US11131706B2

公开(公告)日：2021-09-28

申请号：US14962043

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Keith A. Jenkins

IPC: G01R31/28 ,  G06F30/3312 ,  G01R31/3193 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/30

Abstract: A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

公开(公告)号：US20210239736A1

公开(公告)日：2021-08-05

申请号：US16778746

申请日：2020-01-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHIA-LIN TSAI ,  WUN-YE KU ,  TIEN-YU CHEN ,  CHIA-YI LIN

IPC: G01R1/073 ,  G01R31/3193 ,  G01R31/319 ,  G01R1/067

Abstract: The present disclosure provides a wafer test system and methods thereof. The test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

公开(公告)号：US11038635B2

公开(公告)日：2021-06-15

申请号：US16662785

申请日：2019-10-24

Applicant: Roku, Inc.

Inventor： Nermin Osmanovic

IPC: H04L1/24 ,  H04L1/06 ,  G01R31/28 ,  H04R29/00 ,  G01R31/3193

Abstract: Embodiments described herein generally relate to measuring and evaluating a test signal generated by a device under test (DUT). In particular, the test signal generated by the DUT may be compared to a reference signal and scored based on the comparison. For example, a method may include: capturing a test signal from a device under test; splicing the test signal into a plurality of test audio files based on a plurality of frequency bins; at each frequency bin, comparing each of the plurality of test audio files to a corresponding reference audio file from among a plurality of reference audio files, the plurality of reference audio files being associated with a reference signal; and calculating a performance score of the device under test based on the comparisons.

公开(公告)号：US10976368B2

公开(公告)日：2021-04-13

申请号：US16387912

申请日：2019-04-18

Applicant: SK hynix Inc.

Inventor： Ja Beom Koo

IPC: G01R31/3193 ,  G11C29/02 ,  G11C5/04 ,  G11C29/38

Abstract: A memory device may be provided. The memory device may include a test data output circuit configured to compare lower data output from a lower data storage region with upper data output from an upper data storage region and make a decision. The memory device may include a data transmitter configured to output the lower data by inverting or noninverting the lower data according to the decision. The memory device may include a test control circuit generates a test control signal according to a test read signal and an address signal.