公开(公告)号：US5787299A

公开(公告)日：1998-07-28

申请号：US751281

申请日：1996-11-18

申请人： Farrell L. Ostler ,  Ata R. Khan ,  Gregory K. Goodhue

发明人： Farrell L. Ostler ,  Ata R. Khan ,  Gregory K. Goodhue

IPC分类号： G06F1/22 ,  G06F1/04

CPC分类号： G06F1/22

摘要： A microcontroller with selectable function external pins. Program controllable configuration registers control pin function selection through multiplexers which select between data/address lines and special function unit output lines and which control line drivers which are disabled when the pins are used as input pins.

摘要翻译： 具有可选功能外部引脚的微控制器。 程序可控配置寄存器通过在数据/地址线和特殊功能单元输出线之间进行选择的多路复用器控制引脚功能选择，以及当引脚用作输入引脚时禁用的控制线驱动器。

公开(公告)号：US5656959A

公开(公告)日：1997-08-12

申请号：US562478

申请日：1995-11-24

申请人： Steve Chang ,  Elie Ayache

发明人： Steve Chang ,  Elie Ayache

IPC分类号： G06F1/08 ,  G06F1/10 ,  G06F1/22 ,  H03L7/18 ,  H03B21/00

CPC分类号： G06F1/08 ,  G06F1/10 ,  G06F1/22 ,  H03L7/18

摘要： An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode to accomplish required system functions with a reduced overall pin count.

摘要翻译： 描述了一种改进的时钟合成器系统及其方法，其使用多个双功能引脚在第一操作模式下施加频率选择代码，并且在第二操作模式下发送缓冲的时钟信号，以完成所需的系统功能，并且减少 整体针数。

公开(公告)号：US5414380A

公开(公告)日：1995-05-09

申请号：US47895

申请日：1993-04-19

申请人： Jeffery A. Floyd ,  Lloyd P. Matthews

发明人： Jeffery A. Floyd ,  Lloyd P. Matthews

IPC分类号： G06F3/00 ,  G06F1/22 ,  H03K17/30 ,  H03K19/173 ,  H03K19/003

CPC分类号： G06F1/22 ,  H03K19/1732

摘要： An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

摘要翻译： 集成电路（20）通过在激活复位信号（例如上电复位信号）时感测引脚的焊盘（21）上的逻辑状态来配置输入，输出或输入/输出引脚的有效电平 。 集成电路（20）选择用于提供给内部电路（25）的真或互补信号。 引脚上的电压电平在上电复位信号的有效到无效转换时被锁存。 因此，使用适当的电路板级终端电阻（70,71）将引脚编程到所需的有源逻辑电平，而不需要额外的逻辑电路或专用器件引脚。

公开(公告)号：US5412260A

公开(公告)日：1995-05-02

申请号：US106263

申请日：1993-08-13

申请人： Cyrus Y. Tsui ,  Albert L. Chan ,  Kapil Shankar ,  Ju Shen

发明人： Cyrus Y. Tsui ,  Albert L. Chan ,  Kapil Shankar ,  Ju Shen

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F1/22 ,  G06F11/22 ,  G06F17/50 ,  H03K19/173 ,  H03K19/003

CPC分类号： G06F17/5054 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G06F1/22 ,  H03K19/1732 ,  H03K19/1737

摘要： A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.

摘要翻译： 在使用相同引脚的集成电路中实现系统内编程（ISP）和边界扫描测试的结构和方法来控制这两种功能。 边界扫描测试所需的系统内编程和TDI，TCK，TMS和TDO连接所需的SDI，SCLK，MODE和SDO连接被复用，使得它们由相同的四个引脚提供。 使用系统内编程使能引脚来控制这些引脚的复用。 在替代实施例中，使用相同的引脚和相同的状态机来执行系统内编程和边界扫描测试。 利用IEEE标准1149.1-1990中规定的测试逻辑架构。 为了实现系统内编程指令，Std。 1149.1-1990被修改为包括执行所需编程功能的私有指令。

公开(公告)号：US5182810A

公开(公告)日：1993-01-26

申请号：US359246

申请日：1989-05-31

申请人： James E. Bartling ,  Wendell L. Little ,  Kevin E. Deierling

发明人： James E. Bartling ,  Wendell L. Little ,  Kevin E. Deierling

IPC分类号： G06F1/22 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/22

摘要： A battery-backed ancillary power-management chip, in combination with a battery-backed microprocessor or microcontroller, permits a low-power system to achieve a zero-power standby mode with full nonvolatility. The ancillary chip contains transmission gates which can cut off the connection between two other chips if one of them is turned off. This avoids problems of power leakage, substrate pumping, etc., when two chips which are connected together can be independently powered up or powered down.Also provided is a portable data module, which includes a microprocessor and a large LCD display. The disclosed inventions permit the user to operate the display without powering up the microprocessor (to preserve a complex display, e.g. when the user has provided no inputs for a certain length of time), or to operate the microprocessor without the display (e.g. for data transfer or reduction operations).

摘要翻译： 电池支持的辅助电源管理芯片与电池支持的微处理器或微控制器相结合，允许低功耗系统实现具有完全非易失性的零功耗待机模式。 辅助芯片包含传输门，如果其中一个芯片关闭，它们可以切断两个其他芯片之间的连接。 当连接在一起的两个芯片可以独立上电或断电时，可以避免漏电，基板泵送等问题。 还提供了一种便携式数据模块，其包括微处理器和大型LCD显示器。 所公开的发明允许用户操作显示器而不加电微处理器（以保持复杂的显示，例如当用户在一定时间内没有提供输入）时，或者在没有显示器的情况下操作微处理器（例如，用于数据 转移或还原操作）。

公开(公告)号：US5021996A

公开(公告)日：1991-06-04

申请号：US370063

申请日：1989-06-21

申请人： Nobuhisa Watanabe

发明人： Nobuhisa Watanabe

IPC分类号： G06F11/22 ,  G06F1/22 ,  G06F11/28 ,  G06F11/36 ,  G06F15/78

CPC分类号： G06F1/22

摘要： A microcomputer universal package has testing terminals and switching circuitry for selecting first and second operations. In the first operation, as an evaluator type, a test device is connected to the testing terminals of the package. In the second operation, as a piggyback type, a rewritable ROM (EPROM) is connected to the testing terminals of the package. The testing terminals are automatically switched for the particular operation by the switching circuitry. Accordingly, the same device can be used as the evaluator type chip and the piggyback-type chip, which reduces the time and the cost of developing the program. In addition, since the piggyback-type chip, the evaluator-type chip, and a mask-type ROM chip can be constructed with the same pin arrangement, the program can be evaluated by the evaluator-type chip in the mask-type ROM mounting board that becomes the final product without requiring an interface board.

摘要翻译： 微型计算机通用封装具有用于选择第一和第二操作的测试端子和开关电路。 在第一操作中，作为评估器类型，测试装置连接到包装的测试端子。 在第二操作中，作为搭载型，可重写ROM（EPROM）连接到封装的测试端子。 测试终端由切换电路自动切换到特定的操作。 因此，可以使用相同的装置作为评估器型芯片和背负型芯片，这减少了开发程序的时间和成本。 此外，由于搭载式芯片，评估器型芯片和掩模型ROM芯片可以以相同的引脚布置构成，所以可以通过掩模型ROM安装中的评估器型芯片来评估程序 板，成为最终产品，而不需要接口板。

公开(公告)号：US4746815A

公开(公告)日：1988-05-24

申请号：US881755

申请日：1986-07-03

申请人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

发明人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

IPC分类号： H01L21/82 ,  G06F1/22 ,  H01L21/822 ,  H01L23/538 ,  H01L27/04 ,  H03K3/26 ,  H03K3/335

CPC分类号： G06F1/22 ,  H01L23/5382 ,  H01L2924/0002 ,  Y10T307/492

摘要： A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

摘要翻译： 一种特别设计的模块和集成电路芯片，允许在芯片接收器和驱动器电路之间共享模块EC焊盘。 该芯片具有其中每个接收器电路的直接正常输入线和来自其中每个驱动器电路的直接正常输出线以及从这些电路中的每一个到各种EC焊盘的信号线。 该芯片还包括用于在其正常和EC线路之间切换接收器电路和驱动器电路以实现电子删除功能的开关和控制电路。 在优选实施例中，大部分EC焊盘通过开关和控制电路可切换地连接到不同组的三个相邻接收器电路，驱动电路或其组合。 该设计允许使用模块通常需要的大约一半的EC焊盘，同时允许在大多数情况下同时向三个相邻的接收器或驱动器电路进行EC连接。

公开(公告)号：US4670838A

公开(公告)日：1987-06-02

申请号：US578348

申请日：1984-02-09

申请人： Kazuhide Kawata

发明人： Kazuhide Kawata

IPC分类号： G06F11/22 ,  G06F1/22 ,  G06F9/30 ,  G06F9/38 ,  G06F11/28 ,  G06F11/36 ,  G06F15/78 ,  G06F11/00

CPC分类号： G06F11/3648 ,  G06F1/22 ,  G06F9/30189 ,  G06F9/3879

摘要： A single chip microcomputer responsive to internal and external instructions in normal and debug modes, respectively, comprises a program counter and first, second, third, and fourth port groups in both of the normal and the debug modes. The first through the fourth port groups are operable in the normal mode to process each internal instruction. Master and slave modes are defined in the debug mode to selectively change operations of the first through the fourth port groups by the use of port controllers to process each external instruction. The master mode is specified by using the first and the second groups as an instruction input port group for each external instruction and as a transfer bus for data related to each external instruction, respectively. In contrast, the third and the fourth port groups are used as an instruction input port group and a transfer bus, respectively. The master and the slave modes are indicated through a single terminal used in the normal mode. The program counter may be left unused in the debug mode. A pair of the microcomputers are connected to each other together with an external device for each external instruction, so as to carry out a debug operation. The debug operation can be voluntarily interrupted and stepwise advanced by the use of a specific instruction representative of jump to present address.

摘要翻译： 在正常和调试模式下分别响应于内部和外部指令的单片微计算机包括在正常和调试模式中的程序计数器和第一，第二，第三和第四端口组。 第一至第四端口组可在正常模式下操作以处理每个内部指令。 主模式和从模式在调试模式下定义，以通过使用端口控制器来选择性地更改第一至第四端口组的操作，以处理每个外部指令。 主模式通过使用第一组和第二组作为每个外部指令的指令输入端口组和分别用于与每个外部指令相关的数据的传输总线来指定。 相比之下，第三和第四端口组分别用作指令输入端口组和传输总线。 主模式和从模式通过在正常模式下使用的单个终端指示。 程序计数器可能在调试模式下未使用。 一对微型计算机与每个外部指令的外部设备相互连接，从而进行调试操作。 可以通过使用代表跳转到现在地址的特定指令来自动中断调试操作并逐步提前。

公开(公告)号：US4504926A

公开(公告)日：1985-03-12

申请号：US365894

申请日：1982-04-06

申请人： Shinjiro Toyoda

发明人： Shinjiro Toyoda

IPC分类号： G06F13/10 ,  G06F1/22 ,  G06F15/78 ,  G06F3/00

CPC分类号： G06F1/22

摘要： A mode setting control system comprising a one-chip microprocessor and a mode setting circuit provided outside the microprocessor. The mode setting circuit comprises mode designating switches, diodes and a flip-flop. Data representing the mode designated by the switches is written into the one-chip microprocessor through I/O pins. After the one-chip microprocessor has been brought out of the reset state, an ADR signal is supplied from the one-chip microprocessor through an ADR pin thereof, whichever operation mode the microprocessor is set to. The ADR signal is supplied to the mode setting circuit, thus electrically disconnecting the same from the one-chip microprocessor. Consequently, data other than the mode data can be written into the I/O pins.

摘要翻译： 一种模式设置控制系统，包括设置在微处理器外部的单片微处理器和模式设置电路。 模式设置电路包括模式指定开关，二极管和触发器。 表示由开关指定的模式的数据通过I / O引脚写入单片微处理器。 在单片微处理器已经退出复位状态之后，ADR信号由单片微处理器通过其ADR引脚提供，无论哪个操作模式被设置为微处理器。 ADR信号被提供给模式设置电路，从而将其与单片微处理器电连接。 因此，模式数据以外的数据可以写入I / O引脚。

公开(公告)号：US3939452A

公开(公告)日：1976-02-17

申请号：US378354

申请日：1973-07-11

申请人： Gian Franco Faggian

发明人： Gian Franco Faggian

IPC分类号： G06F9/22 ,  G06F1/12 ,  G06F1/22 ,  G06F9/30 ,  G06F15/02 ,  G06F15/78 ,  G06F15/20 ,  G06F9/06 ,  G06F9/16 ,  G06F13/00

CPC分类号： G06F1/22 ,  G06F1/12 ,  G06F15/7835

摘要： A desk-top electronic computer with MOS circuit logic comprising an input device, an output device and a logic unit adapted to carry out the various operations of the computer. The logic unit is disposed on at least two MOS circuit chips synchronized by a main oscillator. Each MOS chip is provided with a corresponding timing circuit adapted to generate mutually coordinated timing signals. The logic unit includes a read only memory or ROM for storing the microinstructions commanding the various functions, a computing unit and a control unit adapted to permit the selection of the microinstructions from the ROM by addressed access for the purpose of supplying a sequence of microinstructions to the computing unit, access of the address and output of the microinstructions taking place through a single connection between the ROM and the control unit.

摘要翻译： 一种具有MOS电路逻辑的台式电子计算机，包括输入装置，输出装置和适于执行计算机的各种操作的逻辑单元。 逻辑单元设置在由主振荡器同步的至少两个MOS电路芯片上。 每个MOS芯片设置有适于产生相互协调的定时信号的相应的定时电路。 逻辑单元包括用于存储命令各种功能的微指令的只读存储器或ROM，计算单元和控制单元，该计算单元和控制单元适于通过寻址访问来从ROM中选择微指令，以将微指令序列提供给 计算单元，通过ROM和控制单元之间的单个连接进行地址的输入和微指令的输出。