公开(公告)号：US20220262948A1

公开(公告)日：2022-08-18

申请号：US17631287

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Chunxu LI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

公开(公告)号：US11323039B2

公开(公告)日：2022-05-03

申请号：US16959001

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Rongrong Tao ,  Hao Wang ,  Jinyu Xiao ,  Wei Su ,  Shen Xu ,  Longxing Shi

IPC: H02M3/335 ,  H03K5/24 ,  H02M1/00

Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a critical value Tset, calculating a time interval Ttap between adjacent zero points in the current connection time, outputting a shutdown signal at the zero points, and comparing the time interval Ttap with the preset critical value Tset; when Ttap>Tset, controlling the current shutdown time to be less than the shutdown time of the preceding cycle and outputting a start signal; when Ttap=0, controlling the current shutdown time to be greater than the shutdown time of the preceding cycle and outputting a start signal; and when 0

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US11264468B2

公开(公告)日：2022-03-01

申请号：US16772031

申请日：2019-01-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang Wang

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a field oxide layer, a gate region and field plate integrated structure and a plurality of contact holes. A body region and a drift region are formed in the semiconductor substrate. An active region is formed in the body region, and a drain region is formed in the drift region. A field oxide layer is located on the drift region and the drift region surrounds a part of the field oxide layer. An integrated structure including a gate region and a field plate, the integrated structure extending from above the field oxide layer to above the body region. A depth of a contact hole closer to the source region penetrating into the field oxide layer is greater than a depth of a contact hole closer to the drain region penetrating into the field oxide layer.

公开(公告)号：US11201557B2

公开(公告)日：2021-12-14

申请号：US16959116

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Qinsong Qian ,  Shengyou Xu ,  Feng Lin ,  Hao Wang ,  Wei Su ,  Qi Liu ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00

Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

公开(公告)号：US20210358903A1

公开(公告)日：2021-11-18

申请号：US17266134

申请日：2019-11-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866 ,  H01L29/74 ,  H01L21/266

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

公开(公告)号：US11171223B2

公开(公告)日：2021-11-09

申请号：US16957600

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

公开(公告)号：US11164946B2

公开(公告)日：2021-11-02

申请号：US16461721

申请日：2017-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tao Liu ,  Zhibin Liang ,  Song Zhang ,  Yan Jin ,  Dejin Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11517 ,  H01L29/788

Abstract: A manufacturing method for a flash device. A manufacturing method for a flash device, comprising: providing a substrate; forming sequentially, on the substrate, a floating gate (FG) oxide layer, an FG polycrystalline layer, and an FG mask layer; etching, at the FG location region, the FG polycrystalline layer and the FG mask layer, forming a window on the FG mask layer, and forming a trench on the FG polycrystalline layer, the window being communicated with the trench; performing second etching of the side wall of the window of the FG mask layer, enabling the width of the trench located on the FG polycrystalline layer to be less than the width of the secondarily-etched window located on the FG mask layer; and oxidizing the FG polycrystalline layer, enabling the oxide to fill the trench to form a field oxide layer; and etching an FG having sharp angles.

公开(公告)号：US20210313312A1

公开(公告)日：2021-10-07

申请号：US17265541

申请日：2019-09-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866 ,  H01L29/66

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

公开(公告)号：US11088253B2

公开(公告)日：2021-08-10

申请号：US16483396

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.