公开(公告)号：US12224340B2

公开(公告)日：2025-02-11

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang Liu ,  Chi Zhang ,  Kui Xiao ,  Guipeng Sun ,  Dejin Wang ,  Jiaxing Wei ,  Li Lu ,  Weifeng Sun ,  Shengli Lu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US11605641B2

公开(公告)日：2023-03-14

申请号：US17257087

申请日：2019-10-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Song Zhang ,  Zhibin Liang ,  Yan Jin ,  Dejin Wang

IPC: H01L27/11521

Abstract: A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

公开(公告)号：US11894458B2

公开(公告)日：2024-02-06

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing Wei ,  Qichao Wang ,  Kui Xiao ,  Dejin Wang ,  Li Lu ,  Ling Yang ,  Ran Ye ,  Siyang Liu ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/78

CPC classification number: H01L29/7825

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US11515395B2

公开(公告)日：2022-11-29

申请号：US17624336

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Siyang Liu ,  Ningbo Li ,  Dejin Wang ,  Kui Xiao ,  Chi Zhang ,  Sheng Li ,  Xinyi Tao ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/861

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

公开(公告)号：US11770076B2

公开(公告)日：2023-09-26

申请号：US17420866

申请日：2020-06-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Minggang Chen ,  Wanqing Yang ,  Dejin Wang ,  Rui Jiang ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/38 ,  H02M1/34

CPC classification number: H02M3/33569 ,  H02M1/342 ,  H02M1/38 ,  H02M3/33523

Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

公开(公告)号：US11164946B2

公开(公告)日：2021-11-02

申请号：US16461721

申请日：2017-12-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tao Liu ,  Zhibin Liang ,  Song Zhang ,  Yan Jin ,  Dejin Wang

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11517 ,  H01L29/788

Abstract: A manufacturing method for a flash device. A manufacturing method for a flash device, comprising: providing a substrate; forming sequentially, on the substrate, a floating gate (FG) oxide layer, an FG polycrystalline layer, and an FG mask layer; etching, at the FG location region, the FG polycrystalline layer and the FG mask layer, forming a window on the FG mask layer, and forming a trench on the FG polycrystalline layer, the window being communicated with the trench; performing second etching of the side wall of the window of the FG mask layer, enabling the width of the trench located on the FG polycrystalline layer to be less than the width of the secondarily-etched window located on the FG mask layer; and oxidizing the FG polycrystalline layer, enabling the oxide to fill the trench to form a field oxide layer; and etching an FG having sharp angles.