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    Apparatus for providing multiple screens and method of dynamically configuring multiple screens
    192.
    发明申请
    Apparatus for providing multiple screens and method of dynamically configuring multiple screens 有权
    用于提供多个屏幕的设备和动态地配置多个屏幕的方法

    公开(公告)号：US20070052855A1

    公开(公告)日：2007-03-08

    申请号：US11496482

    申请日：2006-08-01

    Applicant: Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn Adams

    Inventor： Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn Adams

    IPC: H04N5/45

    CPC classification number: G09G5/14 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  H04N5/445 ,  H04N5/44591 ,  H04N5/45 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4316 ,  H04N21/443 ,  H04N21/4622

    Abstract: An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus for providing multiple screens includes a digital signal processing module which receives video information, audio information, or data information and restores a service based on the video information, the audio information or the data information, a service processing module which generates a plurality of logical screens and an overlay screen for displaying the restored service, and an output module which maps the plurality of logical screens generated by the service processing module to different locations on a display screen and allows the overlay screen to overlay the display screen.

    Abstract translation: 提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。 用于提供多个屏幕的装置包括：数字信号处理模块，其接收视频信息，音频信息或数据信息，并且基于视频信息，音频信息或数据信息恢复服务;服务处理模块，其生成多个 用于显示恢复的服务的逻辑屏幕和覆盖屏幕;以及输出模块，其将由服务处理模块生成的多个逻辑屏幕映射到显示屏幕上的不同位置，并允许覆盖屏幕覆盖显示屏幕。

    Dual gate CMOS semiconductor devices and methods of fabricating such devices
    194.
    发明申请
    Dual gate CMOS semiconductor devices and methods of fabricating such devices 审中-公开
    双栅极CMOS半导体器件及其制造方法

    公开(公告)号：US20070034966A1

    公开(公告)日：2007-02-15

    申请号：US11477558

    申请日：2006-06-30

    Applicant: Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

    Inventor： Min-Joo Kim ,  Jong-Ho Lee ,  Sung-Kee Han ,  Hyung-Suk Jung

    IPC: H01L29/94

    CPC classification number: H01L21/823842 ,  H01L21/28194 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    Abstract: Disclosed are dual gate CMOS devices and methods for fabricating such devices. The dual gate structures are produced by forming a first gate electrode having first conductive stack on transistors of a first channel type and forming a second gate electrode having a second conductive stack on transistors of a second channel type, wherein the first and second conductive stacks have different compositions for including different work functions (Φ) in the respective transistors. At least one of the first and second conductive stacks will include metal(s) and/or metal compound(s) from which, when subjected to an appropriate thermal treatment, the metal(s) will diffuse to the interface formed between in the gate dielectric layer and the gate electrode and thereby modify the electrical properties of the associated transistors as reflected in, for example, a Vfb shift.

    Abstract translation: 公开了用于制造这种器件的双栅极CMOS器件和方法。 双栅极结构通过在第一沟道型晶体管上形成具有第一导电叠层的第一栅极电极和在第二沟道型晶体管上形成具有第二导电叠层的第二栅极电极而制造，其中第一和第二导电叠层具有 用于在各个晶体管中包括不同功函数（Phi）的不同组合。 第一和第二导电叠层中的至少一个将包括金属和/或金属化合物，当经受适当的热处理时，金属将扩散到在栅极之间形成的界面 电介质层和栅电极，从而改变相关晶体管的电性能，如例如V bias偏移所反映的。

    Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique
    198.
    发明申请
    Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique 审中-公开
    使用原子层沉积技术制造掺杂硅的金属氧化物层的方法

    公开(公告)号：US20060257563A1

    公开(公告)日：2006-11-16

    申请号：US11329696

    申请日：2006-01-11

    Applicant: Seok-Joo Doh ,  Shi-Woo Rhee ,  Jong-Pyo Kim ,  Jung-Hyoung Lee ,  Jong-Ho Lee ,  Yun-Seok Kim

    Inventor： Seok-Joo Doh ,  Shi-Woo Rhee ,  Jong-Pyo Kim ,  Jung-Hyoung Lee ,  Jong-Ho Lee ,  Yun-Seok Kim

    IPC: C23C16/00

    CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531

    Abstract: There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor. The sequence of operations of repeatedly performing the metal oxide layer formation cycle K times, followed by repeatedly performing the silicon-doped metal oxide layer formation cycle Q times, is performed one or more times until a silicon-doped metal oxide layer with a desired thickness is formed on the substrate. In addition, a method of fabricating a silicon-doped hafnium oxide (Si-doped HfO2) layer according to a similar invention method is also provided.

    Abstract translation: 提供了使用原子层沉积技术在半导体衬底上制造掺硅金属氧化物层的方法。 这些方法包括重复进行金属氧化物层形成循环K次的操作和重复进行掺硅金属氧化物层形成循环Q次的操作。 值K和Q中的至少一个是2以上的整数。 K和Q分别为1至约10的整数。 金属氧化物层形成循环包括将金属源气体供给到包含基板的反应器中，然后将氧化物气体注入到反应器中的步骤。 掺杂硅的金属氧化物层形成循环包括将含有硅的金属源气体供给到含有该基板的反应器中，然后将氧化物气体注入反应器。 重复执行金属氧化物层形成循环K次的操作顺序，随后重复进行掺杂硅的金属氧化物层形成循环Q次，执行一次或多次，直到具有所需厚度的掺硅金属氧化物层 形成在基板上。 此外，还提供了根据类似的发明方法制造掺杂硅的氧化铪（Si掺杂的HfO 2 N 2）层的方法。

    Optical printed circuit board and optical interconnection block using optical fiber bundle
    199.
    发明授权
    Optical printed circuit board and optical interconnection block using optical fiber bundle 失效
    光纤印刷电路板和使用光纤束的光互连块

    公开(公告)号：US07136551B2

    公开(公告)日：2006-11-14

    申请号：US11069870

    申请日：2005-03-01

    Applicant: Mu Hee Cho ,  Han Seo Cho ,  Hyo Hoon Park ,  Jong Ho Lee ,  Kyung Rok Kim

    Inventor： Mu Hee Cho ,  Han Seo Cho ,  Hyo Hoon Park ,  Jong Ho Lee ,  Kyung Rok Kim

    IPC: G02B6/42 ,  G02B6/26

    CPC classification number: G02B6/06 ,  G02B6/43 ,  H05K1/0274

    Abstract: Disclosed is an optical printed circuit board (PCB) having a multi-channel optical waveguide, which comprises: an optical waveguide having an optical path for transmitting light beams; a groove for penetrating the optical waveguide; and an optical interconnection block inserted in the groove and connected to the optical waveguide to transmit the light beams, wherein the optical interconnection block includes an optical fiber bundle bent by the angle of 90°. The optical interconnection block connects a plurality of multi-layered optical waveguides to transmit light beams to the optical waveguides. The optical fiber bundle is installed as a medium of the multi-channel optical waveguide in the optical PCB.

    Abstract translation: 公开了一种具有多通道光波导的光学印刷电路板（PCB），其包括：具有用于透射光束的光路的光波导; 用于穿透光波导的凹槽; 以及插入在所述槽中并连接到所述光波导以传输所述光束的光学互连块，其中所述光学互连块包括以90°的角度弯曲的光纤束。 光互连块连接多个多层光波导以将光束传输到光波导。 光纤束作为多路光波导的介质安装在光学PCB中。

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