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1887 records (took 0.029 seconds)

    On-chip resistor trimming to compensate for process variation
    191.
    发明授权
    On-chip resistor trimming to compensate for process variation 有权

    公开(公告)号：US11476018B2

    公开(公告)日：2022-10-18

    申请号：US17385625

    申请日：2021-07-26

    Applicant: STMicroelectronics International N.V.

    Inventor： Mohit Kaushik ,  Anil Kumar

    IPC: H01C17/26 ,  H01L21/66

    Abstract: An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2X−1, each having a resistance equal to R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1, a first of the M resistors having a resistance of R*2Y, a last of the M resistors having a resistance of R*2Y*(2X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

    HIGH FREQUENCY RESOLUTION DIGITAL SINUSOID GENERATOR
    192.
    发明申请
    HIGH FREQUENCY RESOLUTION DIGITAL SINUSOID GENERATOR 有权

    公开(公告)号：US20220321111A1

    公开(公告)日：2022-10-06

    申请号：US17673214

    申请日：2022-02-16

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankur BAL

    IPC: H03K5/02

    Abstract: A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

    Isolation logic test circuit and associated test method
    193.
    发明授权
    Isolation logic test circuit and associated test method 有权

    公开(公告)号：US11442108B1

    公开(公告)日：2022-09-13

    申请号：US17477237

    申请日：2021-09-16

    Applicant: STMicroelectronics International N.V.

    Inventor： Venkata Narayanan Srinivasan ,  Gourav Garg ,  Dhulipalla Phaneendra Kumar

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.

    Fractional-N phase lock loop (PLL) with noise cancelation
    194.
    发明授权
    Fractional-N phase lock loop (PLL) with noise cancelation 有权

    公开(公告)号：US11418200B2

    公开(公告)日：2022-08-16

    申请号：US17507221

    申请日：2021-10-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankit Gupta ,  Sagnik Mukherjee

    IPC: H03L7/089 ,  H03L7/087 ,  H03L7/197

    Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

    HIGH DENSITY ARRAY, IN MEMORY COMPUTING
    195.
    发明申请
    HIGH DENSITY ARRAY, IN MEMORY COMPUTING 有权

    公开(公告)号：US20220238150A1

    公开(公告)日：2022-07-28

    申请号：US17721956

    申请日：2022-04-15

    Applicant: STMicroelectronics International N.V.

    Inventor： Anuj GROVER ,  Tanmoy ROY

    IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

    Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

    Apparatus and method for an analog to digital converter
    196.
    发明授权
    Apparatus and method for an analog to digital converter 有权

    公开(公告)号：US11381207B2

    公开(公告)日：2022-07-05

    申请号：US16838315

    申请日：2020-04-02

    Applicant: STMicroelectronics International N.V.

    Inventor： Riju Biswas

    IPC: H03F3/45 ,  H03M1/12

    Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

    PHASE LOCK LOOP (PLL) WITH OPERATING PARAMETER CALIBRATION CIRCUIT AND METHOD
    198.
    发明申请
    PHASE LOCK LOOP (PLL) WITH OPERATING PARAMETER CALIBRATION CIRCUIT AND METHOD 有权

    公开(公告)号：US20220200607A1

    公开(公告)日：2022-06-23

    申请号：US17519122

    申请日：2021-11-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Ankit GUPTA

    IPC: H03L7/099 ,  H03L7/089 ,  H03L7/093

    Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

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