公开(公告)号：US12189183B2

公开(公告)日：2025-01-07

申请号：US18046189

申请日：2022-10-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Won Suk Lee ,  Andreas D. Stricker

IPC: G02B6/126 ,  G02B6/122 ,  G02B6/27 ,  G02B6/12 ,  G02B6/125

Abstract: A structure includes a polarization device such as a polarization splitter, a polarization combiner or a polarization splitter rotator including a waveguide having a light absorber at an end section with an at least hook shape, e.g., it can be hooked or spiral shape. The structure also includes another waveguide adjacent the stated waveguide. The hook or spiral shape acts as a light absorber that reduces undesired optical noise such as excessive light insertion loss and/or light scattering. The hook or spiral shape may also be used on supplemental waveguides used to further filter and/or refine an optical signal in one of the waveguides of the polarization device, e.g., downstream of an output section of the polarization splitter and/or rotator.

公开(公告)号：US20240427177A1

公开(公告)日：2024-12-26

申请号：US18212437

申请日：2023-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/015 ,  G02F1/025 ,  G02F1/035

Abstract: Plasmonic photonic structures that include a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a waveguide core on a substrate, a first layer that has an overlapping relationship with the first waveguide core, and a second layer that has an overlapping relationship with the first waveguide core and the first layer. The first layer comprises a metal, and the second layer comprising a material that exhibits an electric-field-induced Pockels effect.

公开(公告)号：US20240427095A1

公开(公告)日：2024-12-26

申请号：US18338712

申请日：2023-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ravi Prakash Srivastava ,  Yusheng Bian ,  Vibhor Jain

IPC: G02B6/42

Abstract: Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.

公开(公告)号：US20240427094A1

公开(公告)日：2024-12-26

申请号：US18212754

申请日：2023-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Takako Hirokawa ,  Yusheng Bian ,  Thomas Houghton ,  Kevin Dezfulian ,  Carrie Yurkon

IPC: G02B6/42 ,  G06T7/00

Abstract: Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.

公开(公告)号：US12176351B2

公开(公告)日：2024-12-24

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L27/146 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20240419023A1

公开(公告)日：2024-12-19

申请号：US18209680

申请日：2023-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/035

Abstract: Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.

公开(公告)号：US20240402421A1

公开(公告)日：2024-12-05

申请号：US18802210

申请日：2024-08-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US20240377583A1

公开(公告)日：2024-11-14

申请号：US18196796

申请日：2023-05-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.

公开(公告)号：US20240348005A1

公开(公告)日：2024-10-17

申请号：US18134068

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Yusheng Bian ,  Koushik Ramachandran

IPC: H01S5/024 ,  G02B6/42 ,  H01S5/02345 ,  H01S5/0236 ,  H01S5/0237 ,  H01S5/183

CPC classification number: H01S5/02469 ,  G02B6/4215 ,  H01S5/02345 ,  H01S5/0236 ,  H01S5/0237 ,  H01S5/18305

Abstract: Structures including a photonics chip and a surface-mounted laser chip, and methods of forming same. The structure comprises a photonics chip including a surface, a laser chip including a light output and a body that are spaced from the surface of the photonics chip, a first adhesive between the body of the laser chip and the surface of the photonics chip, and a second adhesive between the body of the laser chip and the surface of the photonics chip. The light output is oriented toward the surface of the photonics chip, the first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity that is less than the first thermal conductivity of the first adhesive, and the second adhesive is disposed in a light path between the light output of the laser chip and the surface of the photonics chip.

公开(公告)号：US20240329308A1

公开(公告)日：2024-10-03

申请号：US18127220

申请日：2023-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arpan Dasgupta ,  Yusheng Bian ,  John M. Safran ,  Norman Robson

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13

Abstract: Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.