公开(公告)号：US11158574B2

公开(公告)日：2021-10-26

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L45/00 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/522

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US20230266544A1

公开(公告)日：2023-08-24

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US11417525B2

公开(公告)日：2022-08-16

申请号：US16154284

申请日：2018-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Martin O'Toole ,  Keith Donegan ,  Brendan O'Brien ,  Hsueh-Chung Chen ,  Terry A. Spooner ,  Craig Child ,  Sean Reidy ,  Ravi Prakash Srivastava ,  Louis Lanzerotti ,  Atsushi Ogino

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

公开(公告)号：US20240361529A1

公开(公告)日：2024-10-31

申请号：US18139128

申请日：2023-04-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Thomas Houghton ,  Yusheng Bian ,  Karen Nummy ,  Kevin Dezfulian ,  Takako Hirokawa

IPC: G02B6/30 ,  G02B6/42

CPC classification number: G02B6/305 ,  G02B6/42 ,  G02B6/4206

Abstract: Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.

公开(公告)号：US20210193584A1

公开(公告)日：2021-06-24

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  H01L21/768

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

公开(公告)号：US20210193573A1

公开(公告)日：2021-06-24

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US20240427094A1

公开(公告)日：2024-12-26

申请号：US18212754

申请日：2023-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Takako Hirokawa ,  Yusheng Bian ,  Thomas Houghton ,  Kevin Dezfulian ,  Carrie Yurkon

IPC: G02B6/42 ,  G06T7/00

Abstract: Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.

公开(公告)号：US11719895B1

公开(公告)日：2023-08-08

申请号：US17679188

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Nicholas Polomoff ,  Keith Donegan ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/42 ,  H01S5/02251 ,  G02B1/00

CPC classification number: G02B6/4212 ,  G02B6/421 ,  G02B6/4245 ,  H01S5/02251 ,  G02B1/002

Abstract: Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

公开(公告)号：US11121087B2

公开(公告)日：2021-09-14

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  G11C5/06

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.