公开(公告)号：US10957694B2

公开(公告)日：2021-03-23

申请号：US16256143

申请日：2019-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith E. Fogel ,  Sivananda K. Kanakasabapathy ,  Alexander Reznicek

IPC: H01L29/161 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

公开(公告)号：US10916552B2

公开(公告)日：2021-02-09

申请号：US16172227

申请日：2018-10-26

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan

IPC: H01L27/11 ,  H01L27/112 ,  H01L27/088

Abstract: A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. The fin structure includes, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion. A lower gate structure having a first threshold voltage contacts a sidewall of the first semiconductor fin portion, and an upper gate structure having a second threshold voltage contacts a sidewall of the second semiconductor fin portion.

公开(公告)号：US10896912B2

公开(公告)日：2021-01-19

申请号：US16359070

申请日：2019-03-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L27/11541 ,  H01L29/788 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

公开(公告)号：US20200303388A1

公开(公告)日：2020-09-24

申请号：US16359070

申请日：2019-03-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L27/11541 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

公开(公告)号：US10756097B2

公开(公告)日：2020-08-25

申请号：US16590199

申请日：2019-10-01

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

IPC: H01L29/78 ,  H01L27/112 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265

Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

公开(公告)号：US10734505B2

公开(公告)日：2020-08-04

申请号：US15828152

申请日：2017-11-30

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Karthik Balakrishnan ,  Jeng-Bang Yau

IPC: H01L29/10 ,  H01L29/737 ,  H01L29/205 ,  H01L29/20 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/66 ,  H01L29/735 ,  H01L29/08

Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.

公开(公告)号：US10734382B2

公开(公告)日：2020-08-04

申请号：US16526320

申请日：2019-07-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/308

Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.

公开(公告)号：US10714593B2

公开(公告)日：2020-07-14

申请号：US16040149

申请日：2018-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/786 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/761

Abstract: A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.

公开(公告)号：US10672865B2

公开(公告)日：2020-06-02

申请号：US16119078

申请日：2018-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L49/02 ,  H01L27/06

Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.

公开(公告)号：US10585063B2

公开(公告)日：2020-03-10

申请号：US16219208

申请日：2018-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ali Afzali-Ardakani ,  Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/417 ,  G01N27/414 ,  G01N27/30 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  G01N27/327

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.