公开(公告)号：US20150098270A1

公开(公告)日：2015-04-09

申请号：US14570577

申请日：2014-12-15

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C17/18 ,  G11C11/40

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

Abstract translation: 一种装置包括半导体晶体管结构。 半导体晶体管结构包括电介质材料，沟道区，栅极，源极重叠区域和漏极重叠区域。 源重叠区域是可偏置的，以使源重叠区域和栅极之间的第一电压差超过电介质材料的击穿电压。 漏极重叠区域是可偏置的，以使漏极重叠区域和栅极之间的第二电压差超过击穿电压。 该装置包括耦合到半导体晶体管的本体的阱线。 该装置包括被配置为向阱管线施加电压以防止沟道区域和栅极之间的击穿状态的电路。

公开(公告)号：US08929167B2

公开(公告)日：2015-01-06

申请号：US13756136

申请日：2013-01-31

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

IPC: G11C29/00 ,  G11C11/00 ,  G11C7/10 ,  G11C29/44 ,  G11C11/16 ,  G11C11/15 ,  G11C11/155 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

公开(公告)号：US08823120B2

公开(公告)日：2014-09-02

申请号：US13959710

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L29/82 ,  G11C11/15

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/12

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract translation: 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

公开(公告)号：US20140219015A1

公开(公告)日：2014-08-07

申请号：US13759310

申请日：2013-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: G11C7/00 ,  G11C11/40

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

Abstract translation: 一种方法包括在包括重叠区域和沟道区域的半导体晶体管结构下产生击穿条件。 通过使半导体晶体管结构的栅极和重叠区域之间的第一电压差超过半导体晶体管结构的击穿电压，同时保持栅极和沟道区域之间的第二电压差小于 击穿电压。

公开(公告)号：US20140217532A1

公开(公告)日：2014-08-07

申请号：US14246165

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ结构上形成第一MTJ盖层。 第一MTJ盖层包括第一非硝化金属。 该方法还包括在第一MTJ盖层上形成第二MTJ盖层。 第二MTJ盖层包括第二非硝化金属。 该方法还包括在第二MTJ盖层上形成顶部电极层。 第二MTJ盖层是导电的并且被配置为减少或防止氧化。

公开(公告)号：US20140211551A1

公开(公告)日：2014-07-31

申请号：US13756136

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

IPC: G11C29/44 ,  G11C11/16

CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

公开(公告)号：US20140203401A1

公开(公告)日：2014-07-24

申请号：US13748768

申请日：2013-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.

Abstract translation: 公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。 在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。 层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

公开(公告)号：US20140147941A1

公开(公告)日：2014-05-29

申请号：US14172208

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US20140038312A1

公开(公告)日：2014-02-06

申请号：US14048918

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02

CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使所述处理器启动所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

公开(公告)号：US20130235656A1

公开(公告)日：2013-09-12

申请号：US13872338

申请日：2013-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: H01L43/02 ,  G11C11/15

CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

Abstract translation: 一种装置包括包括围绕金属垫的底盖层的结构。 该装置还包括磁隧道结（MTJ）装置，其包括耦合到该结构的底部电极。 MTJ装置包括磁性隧道结层，顶部电极和逻辑帽层。 MTJ装置相对于金属垫偏移。