公开(公告)号：US09991285B2

公开(公告)日：2018-06-05

申请号：US14067424

申请日：2013-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L27/12 ,  H01L21/3213 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US09923070B2

公开(公告)日：2018-03-20

申请号：US15051595

申请日：2016-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/41775 ,  H01L21/28512 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.

公开(公告)号：US09917176B2

公开(公告)日：2018-03-13

申请号：US15297105

申请日：2016-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/764 ,  H01L29/40

CPC classification number: H01L29/66795 ,  H01L21/02271 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

公开(公告)号：US09911645B2

公开(公告)日：2018-03-06

申请号：US15394620

申请日：2016-12-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/785

Abstract: A method includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The method includes an adhesion layer formed in the dielectric layer and over the first metal layer, and the adhesion layer is a discontinuous layer. The method includes a second metal layer formed in the dielectric layer, and the adhesion layer is formed between the second metal layer and the dielectric layer. The second metal layer includes a via portion and a trench portion over the via portion, and the trench portion is wider than the via portion.

公开(公告)号：US09876115B2

公开(公告)日：2018-01-23

申请号：US14935115

申请日：2015-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.

公开(公告)号：US09837536B2

公开(公告)日：2017-12-05

申请号：US15208377

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L27/092 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.

公开(公告)号：US20170345759A1

公开(公告)日：2017-11-30

申请号：US15168323

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature.

公开(公告)号：US09799649B2

公开(公告)日：2017-10-24

申请号：US15009760

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin.

公开(公告)号：US20170294436A1

公开(公告)日：2017-10-12

申请号：US15627329

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

公开(公告)号：US09786564B2

公开(公告)日：2017-10-10

申请号：US15253805

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.