公开(公告)号：US07202518B2

公开(公告)日：2007-04-10

申请号：US10877755

申请日：2004-06-25

Applicant: Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

Inventor： Francois Jacquet ,  Philippe Candellier ,  Robin Cerutti ,  Philippe Coronel ,  Pascale Mazoyer

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  G11C11/405 ,  H01L27/108

Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.

Abstract translation: 集成的动态随机存取存储器元件包括两个用于存储两个相应位的单元。 包括源区和漏区。 每个单元包括具有栅极和在源极和漏极区域之间延伸的中间部分的场效应晶体管。 在每个单元的晶体管的中间部分设置有沟道。 偏振电极被放置在两个晶体管的各个中间部分之间。 该极化电极电容耦合到每个晶体管的中间部分，并用于存储第一和第二位。

公开(公告)号：US07200908B2

公开(公告)日：2007-04-10

申请号：US11442420

申请日：2006-05-26

Applicant: Fabrice Cassett ,  Guillaume Bouche ,  Maurice Rivoire

Inventor： Fabrice Cassett ,  Guillaume Bouche ,  Maurice Rivoire

IPC: H01G7/00 ,  H01G5/00

CPC classification number: H01H59/0009 ,  H01G5/16 ,  H01G5/18 ,  H01H2059/0081 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49156

Abstract: A method of making a variable capacitor by forming a grove portion in an insulating substrate, two upper portions of the substrate located on either side of the groove portion forming two lateral edges, a conductive layer covering the inside of the groove portion, a flexible conductive membrane, placed above the groove portion by bearing on the edges, a dielectric layer covering the conductive layer or the membrane to insulate the conductive layer and the membrane, and terminals of application of a voltage between the conductive layer and the membrane, and such that the depth of the groove portion continuously increases from one of the edges to the bottom of the groove portion, and that the conductive layer covers the inside of the groove portion at least to reach one of the two edges, that it may cover.

Abstract translation: 一种通过在绝缘基板中形成槽部来制造可变电容器的方法，位于形成两个侧边缘的槽部分的任一侧上的基板的两个上部，覆盖槽部分内部的导电层，柔性导电 膜，通过承载在边缘上而置于凹槽部分上方，覆盖导电层或膜的电介质层以使导电层和膜绝缘，以及在导电层和膜之间施加电压的端子，使得 凹槽部分的深度从凹槽部分的一个边缘到底部连续地增加，并且导电层至少覆盖凹槽部分的内部，至少可以覆盖两个边缘中的一个。

公开(公告)号：US07199631B2

公开(公告)日：2007-04-03

申请号：US10473057

申请日：2002-04-04

Applicant: Michel Bardouillet ,  Luc Wuidart

Inventor： Michel Bardouillet ,  Luc Wuidart

IPC: H03L7/00

CPC classification number: G11C5/00 ,  G11C8/20 ,  H03K5/15 ,  H03K5/15066

Abstract: The invention concerns a circuit (1) for storing a binary code (B1, B2, Bi-1, Bi, Bn-1, Bn) in an integrated circuit chip, comprising an input terminal (2) applying a signal (E) triggering reading of the code, output terminals (31, 32, 3i-1, 3i, 3n-1, 3n) for delivering said binary code, first electrical paths (P1, P2, Pi, Pn) individually connecting said input terminal to each output terminal, each path inputting a fixed delay in the manufacture of the integrated circuit, and means (4, 51, 52, 5i, 5n) simultaneously integrating the binary states present in output of the electrical paths.

Abstract translation: 本发明涉及一种用于在集成电路芯片中存储二进制码（B 1，B 2，Bi-1，Bi，Bn-1，Bn）的电路（1），包括：输入端（2）施加信号 （P 1，P 2，P 1，P n），用于传送所述二进制码的输出终端（31,32,3 i-1,3i，3n-1,3n） 将所述输入端子单独连接到每个输出端子，在集成电路的制造中输入固定延迟的每个路径以及同时对存在于电气输出端的二进制状态进行积分的装置（4,51,52,5i，5n） 路径。

公开(公告)号：US20070072032A1

公开(公告)日：2007-03-29

申请号：US11529637

申请日：2006-09-28

Applicant: Sebastien Kouassi

Inventor： Sebastien Kouassi

IPC: H01M8/10 ,  H01M4/00 ,  H01M4/88

CPC classification number: C25F3/12 ,  B81B1/00 ,  C25F3/14 ,  H01M8/0232 ,  H01M8/1097 ,  H01M2008/1095

Abstract: A support wafer made of silicon wafer comprising, on a first surface a porous silicon layer having protrusions, porous silicon pillars extending from the porous silicon layer to the second surface of the wafer, in front of each protrusion. Layers constituting a fuel cell can be formed on the support wafer.

Abstract translation: 一种由硅晶片制成的支撑晶片，在第一表面上具有多孔硅层，该多孔硅层具有突起，在每个突出部前面从多孔硅层延伸到晶片的第二表面。 可以在支撑晶片上形成构成燃料电池的层。

公开(公告)号：US07193918B2

公开(公告)日：2007-03-20

申请号：US10766291

申请日：2004-01-26

Applicant: Michel Harrand ,  Joseph Bulone

Inventor： Michel Harrand ,  Joseph Bulone

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract translation: 对动态随机存取存储器的几页内容进行备份，然后尝试快速刷新它们，例如快速刷新两次，一次观察是否会导致错误。 在整个存储器上重复操作。 根据刷新页面上出现的错误次数不同，刷新周期减少或增加。 因此，内存将自己的刷新周期自动调整到需要的时间。

公开(公告)号：US07191340B2

公开(公告)日：2007-03-13

申请号：US10269098

申请日：2002-10-10

Applicant: Luc Wuidart ,  Michel Bardouillet ,  Laurent Plaza

Inventor： Luc Wuidart ,  Michel Bardouillet ,  Laurent Plaza

IPC: G06F11/30 ,  H04L9/00 ,  G07C9/00 ,  G07B15/00 ,  H04L9/32

CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G07F7/082 ,  H01L23/576 ,  H01L2223/5444 ,  H01L2924/0002 ,  H04L9/0866 ,  H01L2924/00

Abstract: A method and a circuit for generating a secret quantity based on an identifier of an integrated circuit, in which a first digital word is generated from a physical parameter network, and this first word is submitted to at least one retroaction shift register, the output of the shift register forming the secret quantity.

Abstract translation: 一种用于基于从物理参数网络生成第一数字字的集成电路的标识符来生成秘密量的方法和电路，并且该第一个字被提交给至少一个追溯移位寄存器，其输出 移位寄存器形成秘密数量。

公开(公告)号：US07189955B2

公开(公告)日：2007-03-13

申请号：US11127766

申请日：2005-05-11

Applicant: Laurent Simony

Inventor： Laurent Simony

IPC: H01L27/00 ,  H04N5/217

CPC classification number: H04N5/365 ,  H04N5/363

Abstract: A device for correcting the reset noise and/or the fixed pattern noise of an active pixel comprising a photosensitive element, the device comprising a transmission circuit connecting the photosensitive element to a correction node and operating with a first or a second transmission gain; a circuit for providing a correction voltage equal to the sum of a constant voltage and of the noise multiplied by an amplification gain equal to the inverse of the difference between the first and second transmission gains; and a correction circuit capable of bringing the correction node from the constant voltage to the correction voltage, the transmission circuit having the first transmission gain, and of bringing the correction node to the constant voltage, the transmission circuit having the second transmission gain.

Abstract translation: 一种用于校正包括感光元件的有源像素的复位噪声和/或固定图案噪声的装置，该装置包括将感光元件连接到校正节点并以第一或第二传输增益操作的传输电路; 用于提供等于恒定电压和噪声之和乘以与第一和第二传输增益之间的差的倒数的放大增益的和的校正电压的电路; 以及校正电路，其能够将来自所述恒定电压的所述校正节点从所述校正电压引起，所述发送电路具有所述第一发送增益，并且使所述校正节点达到所述恒定电压，所述发送电路具有所述第二发送增益。

公开(公告)号：US20070053233A1

公开(公告)日：2007-03-08

申请号：US11468257

申请日：2006-08-29

Applicant: David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

Inventor： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

IPC: G11C7/00

CPC classification number: G11C16/344 ,  G11C16/0433

Abstract: A method checks the state of a set of memory cells of a memory comprising memory cells arranged in a memory array, means for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive or non-conductive. The method includes features wherein all the memory cells of a set grouping together several memory cells are selected, and then simultaneously coupled to the sense amplifier, and the sense amplifier supplies a global state of all the selected memory cells to which it is coupled, if the latter are simultaneously non-conductive. Application is provided to the checking of a command for block-erasing a memory.

Abstract translation: 一种方法检查包括存储器阵列中布置的存储单元的存储器组的集合的状态，用于选择存储单元的装置以及用于根据所选存储单元是否提供所选存储单元的状态的读出放大器 是导电或不导电的。 该方法包括其中选择分组在一起的几个存储器单元的集合的所有存储单元，然后同时耦合到读出放大器的特征，并且读出放大器提供与其耦合到的所有选定存储单元的全局状态，如果 后者同时不导电。 提供了用于检查用于块擦除存储器的命令的应用。

公开(公告)号：US07184299B2

公开(公告)日：2007-02-27

申请号：US10726263

申请日：2003-12-02

Applicant: Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C11/00

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

公开(公告)号：US07178113B2

公开(公告)日：2007-02-13

申请号：US10473058

申请日：2002-04-04

Applicant: Michel Bardouillet ,  Luc Wuidart

Inventor： Michel Bardouillet ,  Luc Wuidart

IPC: G06F17/50 ,  H03K19/173

CPC classification number: G11C5/00 ,  G11C8/20 ,  H03K5/15066 ,  H03K5/19

Abstract: The invention concerns an identification method and circuit (1) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal (2) for applying a signal (E) triggering an identification, the output terminals (31, 32, 3i−1, 3i, 3n−1, 3n) adapted to deliver a binary identifying code (B1, B2, Bi−1, Bi, Bn−1, Bn), first electrical paths P1, P2, Pi, Pn), individually connecting said input terminal to each output terminal, and means (4, 51, 52, 5i, 5n) for simultaneously integrating the binary states present in output of the electrical paths, each path inputting a delay sensitive to technological dispersions and/or of the integrated circuit fabrication method.

Abstract translation: 本发明涉及包含在集成电路芯片中的网络类型参数的识别方法和电路（1），包括用于施加触发识别的信号（E）的单个输入端子（2），输出端子（3 _{，5 ，5 < 对技术分散和/或集成电路制造方法敏感的延迟。}