Abstract:
Provided is a motor having a magnetic polar unit in which a permanent magnetic polar array having arranged therein alternately a plurality of permanent magnetic polar elements in alternate opposite poles is made to face a plurality of electromagnetic coil arrays alternately excited at opposite poles, and the permanent magnetic polar array is made to move thereby; wherein the motor further comprises a sensor for detecting the periodical magnetic change accompanying the movement of the permanent magnetic polar array, the output of the sensor is directly returned as a direct drive waveform to the electromagnetic coils, and this drive circuit forms the excitation signal based on the return signal.
Abstract:
Provided is a motor having a combination of a plurality of coil pairs and a permanent magnet, wherein these coil pairs are supplied with an excitation signal from a drive circuit so as to be excited at alternate opposite poles, and the permanent magnet is constituted such that the plurality of polar elements is disposed to become alternating opposite poles; the drive circuit is constituted to supply an excitation signal having a prescribed frequency to the coil pairs, and relatively move the coil pairs and permanent magnet with the magnetic attraction repulsion between the coils and permanent magnet; and the drive circuit is constituted to supply to the coil pairs a waveform signal corresponding to the pattern of the back electromotive voltage to be generated in accordance with the relative movement between the coil pairs and permanent magnet.
Abstract:
The present invention is a drive control device for controlling an electric rotational actuator which moves the driver, including: a reference comparison signal generation circuit; a detection circuit for detecting the speed of the actuator and outputting this as a detection signal; a speed designation circuit of the actuator; a rotation control circuit of the actuator; and a phase comparison circuit for comparing the phase of the reference comparison signal and the phase of the detection signal and outputting the comparison result to the rotation control circuit; wherein the rotation control circuit controls the speed of the actuator to conform with the speed designation based on the phase comparison result.
Abstract:
When image reduction is effected at the writing of the image to a frame memory, a first image portion which is to be dropped by the reduction is subjected to weighted-averaging with a second image portion adjacent thereto to modify the second image portion. When an image read from the frame memory is enlarged, a first image portion which is to be added by the enlargement is generated by weighted-averaging two second image portions located before and after the first image portion. When an image is enlarged, it is enlarged by a first enlargement factor in the range of 1 to 2 and enlarged by a second enlargement factor that is an integer, thereby obtaining a result image enlarged by a third enlargement factor that is the product of the first and second enlargement factors.
Abstract:
A video signal of a still image is written into a still image area SIA in a video memory 310, whereas a video signal of a moving picture is written into a moving picture area MIA in the video memory 310. A video signal is read out from the video memory 310 while scaling up or down the video image, and the scaled video signal is then supplied to a display device. This enables a scaled moving picture and a scaled still image to be displayed on the display device.
Abstract:
While a image is displayed on a color monitor 44 based on a first digital video signal DRGB1 output from a first A-D converter 52, a second digital video signal DRGB2 output from a second A-D converter 54 is compressed to capture the image. The image represented by the compressed video data has a smaller size than the original image. In restoration of the image, a video decompressing unit 66 enlarges the size of the image and displays an enlarged image on the color monitor 44.
Abstract:
A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.
Abstract:
The present invention realizes high-speed transfer of video data into a video memory. Addresses used in DMA transfer operation are calculated by simple arithmetic operation in a DMA address operation unit of a DMA controller. Video data are transferred according to the addresses at a high speed to an arbitrary position in a VRAM. An FIFO memory unit can expand and reduce a video image by desirable magnifications in both vertical and horizontal directions during DMA transfer of video data.
Abstract:
A reference value memory circuit 552 in a video switch control circuit 550 stores upper threshold values DU and lower threshold values DL of respective colors defining a predetermined range of chromaticity. A color comparator circuit 554 compares these upper threshold values DU and the lower threshold values DL with a second video signal LSMEM. When a color represented by the second video signal is within the predetermined range of chromaticity, a color comparison signal S1, which is an output of the color comparator circuit 554, becomes at H level, while the color comparison signal S1 becomes at L level when the color is out of the predetermined range of chromaticity. A selection signal S2 is generated according to the color comparison signal S1 and a switcher signal CNT. A video switch 510 selects one of a first video signal LSPC output from a computer and a second video signal LSDA output from a video memory 310 in response to the selection signal S2. As a result, only a desirable portion of the second video image is superimposed over the first video image.
Abstract:
A video multiplexing system for superimposition of scalable video data streams upon a background data stream has a video decoder to extract a first luminance signal, an A/D converter to convert the first luminance signal to digital form, a three-port video memory for storing the digitized luminance signal, a D/A converter for receiving the stored digitized luminance signal and converting it to analog form, a mixing, or multiplexing means, having one input coupled to the D/A converter output, at least one other luminance signal source as an input and control inputs for directing the selection of one of the input luminance signals as an output, and a control means such as a microprocessor for controlling the various components. The write operations to the video memory are synchronized to the incoming luminance signal, and the read operations from video memory are synchronized to the display device. This video multiplexing architecture provides the ability to open a viewport of arbitrary size at any position within a larger display. Scaling of the digitized luminance signal to fit an a viewport of arbitrary size is achieved by varying the frequency of the A/D converter clocks so as to expand or shrink the resulting image.