公开(公告)号：US20050200213A1

公开(公告)日：2005-09-15

申请号：US11078960

申请日：2005-03-11

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H02K29/08 ,  H02K3/00 ,  H02K21/00 ,  H02K41/03 ,  H02P3/18 ,  H02P6/24 ,  H02P7/00 ,  H02P25/06

CPC classification number: H02P6/16 ,  H02P6/28

Abstract: Provided is a motor having a magnetic polar unit in which a permanent magnetic polar array having arranged therein alternately a plurality of permanent magnetic polar elements in alternate opposite poles is made to face a plurality of electromagnetic coil arrays alternately excited at opposite poles, and the permanent magnetic polar array is made to move thereby; wherein the motor further comprises a sensor for detecting the periodical magnetic change accompanying the movement of the permanent magnetic polar array, the output of the sensor is directly returned as a direct drive waveform to the electromagnetic coils, and this drive circuit forms the excitation signal based on the return signal.

Abstract translation: 提供一种具有磁极单元的电动机，其中在其中交替布置有交替相对极的多个永磁极性元件的永磁极性阵列被制成面对在相对极交替地激发的多个电磁线圈阵列，并且永磁体 使磁极阵列移动; 其特征在于，所述电动机还包括用于检测伴随所述永久磁极阵列移动的周期性磁变化的传感器，所述传感器的输出作为直接驱动波形直接返回到所述电磁线圈，并且所述驱动电路基于所述激励信号 在返回信号。

公开(公告)号：US20050194918A1

公开(公告)日：2005-09-08

申请号：US11070406

申请日：2005-03-01

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H02K1/27 ,  H02K21/24 ,  H02K37/00 ,  H02M7/48 ,  H02P1/00 ,  H02P27/06

CPC classification number: H02P6/10 ,  H02P6/16

Abstract: Provided is a motor having a combination of a plurality of coil pairs and a permanent magnet, wherein these coil pairs are supplied with an excitation signal from a drive circuit so as to be excited at alternate opposite poles, and the permanent magnet is constituted such that the plurality of polar elements is disposed to become alternating opposite poles; the drive circuit is constituted to supply an excitation signal having a prescribed frequency to the coil pairs, and relatively move the coil pairs and permanent magnet with the magnetic attraction repulsion between the coils and permanent magnet; and the drive circuit is constituted to supply to the coil pairs a waveform signal corresponding to the pattern of the back electromotive voltage to be generated in accordance with the relative movement between the coil pairs and permanent magnet.

Abstract translation: 提供了具有多个线圈对和永磁体的组合的电动机，其中这些线圈对被提供有来自驱动电路的激励信号，以便在交替的相对极处被激励，并且永磁体被构造成使得 多个极性元件被设置为变成交替的相反极; 驱动电路构成为向线圈对提供具有规定频率的激励信号，并且通过线圈与永久磁铁之间的磁吸引力排斥使线圈对和永久磁铁相对移动; 并且驱动电路被构造成向线圈对提供与根据线圈对和永磁体之间的相对运动而产生的反电动势电压的模式相对应的波形信号。

公开(公告)号：US06885160B2

公开(公告)日：2005-04-26

申请号：US10126960

申请日：2002-04-22

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: B60L11/18 ,  B60L15/20 ,  B62D11/04 ,  B62D11/18

CPC classification number: B60L15/2036 ,  B60L11/1805 ,  B60L2200/22 ,  B62D11/04 ,  B62D11/183 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/7275 ,  Y10S388/911

Abstract: The present invention is a drive control device for controlling an electric rotational actuator which moves the driver, including: a reference comparison signal generation circuit; a detection circuit for detecting the speed of the actuator and outputting this as a detection signal; a speed designation circuit of the actuator; a rotation control circuit of the actuator; and a phase comparison circuit for comparing the phase of the reference comparison signal and the phase of the detection signal and outputting the comparison result to the rotation control circuit; wherein the rotation control circuit controls the speed of the actuator to conform with the speed designation based on the phase comparison result.

Abstract translation: 本发明是一种用于控制驱动器移动的电动旋转致动器的驱动控制装置，包括：参考比较信号发生电路; 用于检测致动器的速度并将其输出作为检测信号的检测电路; 致动器的速度指定电路; 致动器的旋转控制电路; 以及相位比较电路，用于比较参考比较信号的相位和检测信号的相位，并将比较结果输出到旋转控制电路; 其中旋转控制电路基于相位比较结果控制致动器的速度与速度指定一致。

公开(公告)号：US6141061A

公开(公告)日：2000-10-31

申请号：US969944

申请日：1997-11-25

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06T3/40 ,  H04N5/262 ,  H04N9/74

CPC classification number: G06T3/4023 ,  H04N5/2628

Abstract: When image reduction is effected at the writing of the image to a frame memory, a first image portion which is to be dropped by the reduction is subjected to weighted-averaging with a second image portion adjacent thereto to modify the second image portion. When an image read from the frame memory is enlarged, a first image portion which is to be added by the enlargement is generated by weighted-averaging two second image portions located before and after the first image portion. When an image is enlarged, it is enlarged by a first enlargement factor in the range of 1 to 2 and enlarged by a second enlargement factor that is an integer, thereby obtaining a result image enlarged by a third enlargement factor that is the product of the first and second enlargement factors.

公开(公告)号：US5990860A

公开(公告)日：1999-11-23

申请号：US684483

申请日：1996-07-19

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H04N5/262 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/377 ,  G09G5/391 ,  G09G5/395 ,  H04N5/907 ,  H04N5/445

CPC classification number: G09G5/395 ,  G09G5/391 ,  G09G2340/125 ,  H04N5/45 ,  H04N5/907

Abstract: A video signal of a still image is written into a still image area SIA in a video memory 310, whereas a video signal of a moving picture is written into a moving picture area MIA in the video memory 310. A video signal is read out from the video memory 310 while scaling up or down the video image, and the scaled video signal is then supplied to a display device. This enables a scaled moving picture and a scaled still image to be displayed on the display device.

Abstract translation: 静止图像的视频信号被写入视频存储器310中的静止图像区域SIA，而运动图像的视频信号被写入视频存储器310中的运动图像区域MIA。视频信号从 视频存储器310同时向上或向下缩放视频图像，然后将缩放的视频信号提供给显示装置。 这使得缩放的运动图像和缩放的静止图像能够显示在显示装置上。

公开(公告)号：US5689436A

公开(公告)日：1997-11-18

申请号：US496676

申请日：1995-06-29

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: H04N7/26 ,  G06K15/02 ,  G06T3/40 ,  G06T9/00 ,  G09G5/36 ,  H04N7/46 ,  G06K15/00

CPC classification number: H04N19/59 ,  G06K15/02 ,  H04N21/4143 ,  G06K2215/0091

Abstract: While a image is displayed on a color monitor 44 based on a first digital video signal DRGB1 output from a first A-D converter 52, a second digital video signal DRGB2 output from a second A-D converter 54 is compressed to capture the image. The image represented by the compressed video data has a smaller size than the original image. In restoration of the image, a video decompressing unit 66 enlarges the size of the image and displays an enlarged image on the color monitor 44.

Abstract translation: 当基于从第一A-D转换器52输出的第一数字视频信号DRGB1，在彩色监视器44上显示图像时，从第二A-D转换器54输出的第二数字视频信号DRGB2被压缩以捕捉图像。 由压缩视频数据表示的图像具有比原始图像更小的尺寸。 在恢复图像时，视频解压缩单元66放大图像的尺寸并在彩色监视器44上显示放大的图像。

公开(公告)号：US5680178A

公开(公告)日：1997-10-21

申请号：US452012

申请日：1995-05-26

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G09G1/16 ,  G09G3/20 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  H04N5/44 ,  H04N5/445 ,  H04N5/45 ,  H04N9/64 ,  H04N9/74

CPC classification number: G09G1/167 ,  G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  H04N21/4143 ,  H04N5/44 ,  H04N5/44504 ,  H04N5/45 ,  H04N9/641 ,  G09G2340/0435 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2360/126 ,  G09G5/001 ,  G09G5/008 ,  G09G5/363 ,  G09G5/393 ,  H04N5/4401

Abstract: A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.

Abstract translation: 一种包括微处理器，耦合到微处理器的总线，耦合到总线的视频存储器和显示装置的计算机系统。 还提供一个写入控制器，其耦合到总线，并且通过向视频存储器提供写入地址来控制将图像信号写入视频存储器。 写入控制器根据由微处理器设置的多个写入地址参数来改变写入地址的范围，使得要写入图像信号的视频存储器的存储器区域根据 写地址。 此外，由要写入视频存储器的图像信号表示的图像的尺寸改变。 还提供读控制器并且耦合到总线，用于通过与写入到视频存储器异步地向视频存储器提供读地址，并且与提供的同步信号同步地控制从视频存储器读出图像信号 与从视频存储器读出的图像信号一起到显示装置。

公开(公告)号：US5585864A

公开(公告)日：1996-12-17

申请号：US266676

申请日：1994-06-28

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G06F13/28 ,  G09G5/02 ,  G09G5/393 ,  H04N7/26

CPC classification number: G06F13/28 ,  G09G5/022 ,  G09G5/393

Abstract: The present invention realizes high-speed transfer of video data into a video memory. Addresses used in DMA transfer operation are calculated by simple arithmetic operation in a DMA address operation unit of a DMA controller. Video data are transferred according to the addresses at a high speed to an arbitrary position in a VRAM. An FIFO memory unit can expand and reduce a video image by desirable magnifications in both vertical and horizontal directions during DMA transfer of video data.

Abstract translation: 本发明实现了将视频数据高速传输到视频存储器中。 在DMA传输操作中使用的地址通过DMA控制器的DMA地址操作单元中的简单算术运算来计算。 视频数据根据地址高速传送到VRAM中的任意位置。 FIFO存储器单元可以在视频数据的DMA传输期间在垂直和水平方向上扩展和缩小视频图像。

公开(公告)号：US5523958A

公开(公告)日：1996-06-04

申请号：US74675

申请日：1993-06-10

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G09G5/02 ,  H04N11/06 ,  H04N11/20

CPC classification number: G09G5/02 ,  G09G2340/12

Abstract: A reference value memory circuit 552 in a video switch control circuit 550 stores upper threshold values DU and lower threshold values DL of respective colors defining a predetermined range of chromaticity. A color comparator circuit 554 compares these upper threshold values DU and the lower threshold values DL with a second video signal LSMEM. When a color represented by the second video signal is within the predetermined range of chromaticity, a color comparison signal S1, which is an output of the color comparator circuit 554, becomes at H level, while the color comparison signal S1 becomes at L level when the color is out of the predetermined range of chromaticity. A selection signal S2 is generated according to the color comparison signal S1 and a switcher signal CNT. A video switch 510 selects one of a first video signal LSPC output from a computer and a second video signal LSDA output from a video memory 310 in response to the selection signal S2. As a result, only a desirable portion of the second video image is superimposed over the first video image.

Abstract translation: 视频切换控制电路550中的参考值存储电路552存储定义了预定的色度范围的各种颜色的上阈值DU和下阈值DL。 颜色比较器电路554将这些上阈值DU和下阈值DL与第二视频信号LSMEM进行比较。 当由第二视频信号表示的颜色在预定的色度范围内时，作为颜色比较器电路554的输出的颜色比较信号S1变为H电平，而当颜色比较信号S1变为L电平时 颜色超出了预定的色度范围。 根据颜色比较信号S1和切换器信号CNT产生选择信号S2。 视频开关510响应于选择信号S2，选择从计算机输出的第一视频信号LSPC和从视频存储器310输出的第二视频信号LSDA中的一个。 结果，仅第二视频图像的期望部分叠加在第一视频图像上。

公开(公告)号：US5387945A

公开(公告)日：1995-02-07

申请号：US185155

申请日：1994-01-24

Applicant: Kesatoshi Takeuchi

Inventor： Kesatoshi Takeuchi

IPC: G09G1/16 ,  G09G3/20 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  H04N5/44 ,  H04N5/445 ,  H04N5/45 ,  H04N9/64 ,  H04N5/262

CPC classification number: G09G1/167 ,  G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  H04N21/4143 ,  H04N5/44 ,  H04N5/44504 ,  H04N5/45 ,  H04N9/641 ,  G09G2340/0435 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2360/126 ,  G09G5/001 ,  G09G5/008 ,  G09G5/363 ,  G09G5/393 ,  H04N5/4401

Abstract: A video multiplexing system for superimposition of scalable video data streams upon a background data stream has a video decoder to extract a first luminance signal, an A/D converter to convert the first luminance signal to digital form, a three-port video memory for storing the digitized luminance signal, a D/A converter for receiving the stored digitized luminance signal and converting it to analog form, a mixing, or multiplexing means, having one input coupled to the D/A converter output, at least one other luminance signal source as an input and control inputs for directing the selection of one of the input luminance signals as an output, and a control means such as a microprocessor for controlling the various components. The write operations to the video memory are synchronized to the incoming luminance signal, and the read operations from video memory are synchronized to the display device. This video multiplexing architecture provides the ability to open a viewport of arbitrary size at any position within a larger display. Scaling of the digitized luminance signal to fit an a viewport of arbitrary size is achieved by varying the frequency of the A/D converter clocks so as to expand or shrink the resulting image.

Abstract translation: 用于将可分级视频数据流叠加在背景数据流上的视频多路复用系统具有提取第一亮度信号的视频解码器，将第一亮度信号转换为数字形式的A / D转换器，用于存储的三端口视频存储器 数字化亮度信号，用于接收存储的数字化亮度信号并将其转换成模拟形式的D / A转换器，混合或多路复用装置，其具有耦合到D / A转换器输出的一个输入，至少一个其它亮度信号源 作为用于将输入亮度信号之一的选择作为输出的输入和控制输入，以及用于控制各种组件的诸如微处理器的控制装置。 对视频存储器的写入操作与输入的亮度信号同步，并且来自视频存储器的读取操作与显示设备同步。 该视频复用架构提供了在更大的显示器内的任何位置打开任意大小的视口的能力。 通过改变A / D转换器时钟的频率来扩展或缩小所得到的图像来实现数字化亮度信号的调整以适合任意尺寸的视口。