公开(公告)号：US10234892B2

公开(公告)日：2019-03-19

申请号：US15910875

申请日：2018-03-02

Applicant: INPHI CORPORATION

Inventor： Tomas Alexander Dusatko

IPC: G06F1/10 ,  H01L23/66 ,  H01F17/00 ,  H03H7/01 ,  H03H11/28 ,  H03H7/09 ,  H03H7/38

Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.

公开(公告)号：US10230584B1

公开(公告)日：2019-03-12

申请号：US15201295

申请日：2016-07-01

Applicant: INPHI CORPORATION

Inventor： Hari Shankar ,  Ariel Nachum ,  Ariel Leonardo Vera Villarroel

IPC: H04L27/34 ,  H04L12/24

Abstract: Systems and methods for dynamic multitone simulation scenario planning. A method commences upon accessing a server in a circuit simulation environment to generate a multitone simulation signal to accurately simulate non-linear circuit characteristics. The tones of the multitone simulation signal are derived from a subset of possible tones based on certain properties. Some properties serve to eliminate harmonic and intermodulation products that conflict with the tones in the subset. The amplitude and phase for each tone is determined based on certain constraints. A multitone transient signal is generated from the selected tone subset and associated tone attributes to facilitate a circuit simulation. Characteristics of the multitone transient signal and/or simulation results from the circuit simulation can be analyzed to facilitate dynamically planning simulation scenarios that use multitone simulation signals.

公开(公告)号：US20190044653A1

公开(公告)日：2019-02-07

申请号：US16155610

申请日：2018-10-09

Applicant: INPHI CORPORATION

Inventor： Benjamin P. SMITH ,  Arash FARHOODFAR

IPC: H04L1/00 ,  H03M13/29 ,  H04B10/54 ,  H04B10/532 ,  H04B10/516 ,  H04B10/50 ,  H04B10/69

CPC classification number: H04L1/0044 ,  H03M13/2906 ,  H04B10/50 ,  H04B10/516 ,  H04B10/5161 ,  H04B10/532 ,  H04B10/541 ,  H04B10/697 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/006 ,  H04L1/0065

Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.

公开(公告)号：US20190020356A1

公开(公告)日：2019-01-17

申请号：US16134311

申请日：2018-09-18

Applicant: INPHI CORPORATION

Inventor： Arash FARHOODFAR ,  Frank R. KSCHISCHANG ,  Benjamin P. SMITH ,  Andrew HUNT

IPC: H03M13/27 ,  H04L1/00 ,  H03M13/00

CPC classification number: H03M13/2778 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2742 ,  H03M13/2757 ,  H03M13/2767 ,  H03M13/2782 ,  H03M13/6502 ,  H04L1/0071

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

公开(公告)号：US10177851B2

公开(公告)日：2019-01-08

申请号：US15647765

申请日：2017-07-12

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Paul Voois ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Norman L. Swenson ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Vadim Gutnik ,  Adrián Ulises Morales ,  Martin Ignacio Del Barco ,  Martin Carlos Asinari ,  Federico Nicolas Paredes ,  Alfredo Javier Taddei ,  Mauro Marcelo Bruni ,  Damian Alfonso Morero ,  Facundo Abel Alcides Ramos ,  María Laura Ferster ,  Elvio Adrian Serrano ,  Pablo Gustavo Quiroga ,  Roman Antonio Arenas ,  Matias German Schnidrig ,  Alejandro Javier Schwoykoski

IPC: H04B10/00 ,  H04B10/516 ,  H04B10/40 ,  H04B10/61 ,  H04L7/00

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US10164715B2

公开(公告)日：2018-12-25

申请号：US16011470

申请日：2018-06-18

Applicant: INPHI CORPORATION

Inventor： Damian Alfonso Morero ,  Martin Carlos Asinari ,  Martin Ignacio Del Barco ,  Mario Rafael Hueda ,  Lucas Javier Yoaquino

IPC: H04B10/2513 ,  H04L27/06 ,  H04B10/61 ,  H04L25/06

Abstract: An adaptive demapper adaptively demaps an input symbol. An input symbol is received and demapped in a hard-output demapper to generate a current detected symbol corresponding to a constellation point on a current constellation closest to the input symbol. A corrected inverse of a current noise power estimate is determined by updating a previous noise power estimate based on a difference between the input symbol and the current detected symbol. In a soft-output demapper, a log likelihood ratio corresponding to the current detected symbol is determined based on the corrected inverse of the current noise power estimate. The constellation point in the current constellation corresponding to the current detected symbol is then updated to generate an updated constellation based on a difference between the constellation point and the received input symbol.

公开(公告)号：US20180343062A1

公开(公告)日：2018-11-29

申请号：US16054818

申请日：2018-08-03

Applicant: INPHI CORPORATION

Inventor： Paul VOOIS ,  Diego Ernesto CRIVELLI ,  Ramiro Rogelio LOPEZ ,  Jorge Manuel FINOCHIETTO ,  Oscar Ernesto AGAZZI ,  Nariman YOUSEFI ,  Norman L. SWENSON

IPC: H04B10/40 ,  H04B10/2507 ,  H04B10/58

Abstract: Methods of operating an optical communication system in coherent optical transmissions for metro applications. Relative to conventional solutions, the optical communication system can be implemented with reduced cost and can operate with reduced power consumption, while maintaining high data rate performance (e.g., 100G). Furthermore, a programmable transceiver enables compatibility with a range of different types of optical networks having varying performance and power tradeoffs. In one embodiment, the optical communication system uses 100 Gb/s dual-polarization 16-point quadrature amplitude modulation (DP-16QAM) with non-linear pre-compensation of Indium Phosphide (InP) optics for low power consumption.

公开(公告)号：US10133004B2

公开(公告)日：2018-11-20

申请号：US15928732

申请日：2018-03-22

Applicant: INPHI CORPORATION

Inventor： Masaki Kato ,  Radhakrishnan L. Nagarajan

IPC: G02B6/30 ,  G02B6/26 ,  G02B6/122 ,  G02B6/136 ,  G02B6/12

Abstract: An apparatus for converting fiber mode to waveguide mode. The apparatus includes a silicon substrate member and a dielectric member having an elongated body. Part of the elongated body from a back end overlies the silicon substrate member and remaining part of the elongated body up to a front end is separated from the silicon substrate member by a second dielectric material at an under region. The apparatus also includes a waveguide including a segment from the back end to a tail end formed on the dielectric member at least partially overlying the remaining part of the elongated body. The segment is buried in a cladding overlying entirely the dielectric member. The cladding has a refractive index that is less than the waveguide but includes an index-graded section with decreasing index that is formed at least over the segment from the tail end toward the back end.

公开(公告)号：US20180331817A1

公开(公告)日：2018-11-15

申请号：US16028229

申请日：2018-07-05

Applicant: INPHI CORPORATION

Inventor： Parmanand MISHRA ,  Simon FOREY

IPC: H04L7/033 ,  H03L7/00 ,  H04L12/26 ,  H04L27/01 ,  H04L25/02 ,  H04B17/318 ,  H04L7/00 ,  H03M9/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03M9/00 ,  H04B17/318 ,  H04L7/0083 ,  H04L7/0091 ,  H04L7/033 ,  H04L25/0262 ,  H04L27/01 ,  H04L43/04 ,  H04L43/16

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

公开(公告)号：US10128827B1

公开(公告)日：2018-11-13

申请号：US15343608

申请日：2016-11-04

Applicant: INPHI CORPORATION

Inventor： Irene Quek

IPC: H03K5/135 ,  H03M1/86 ,  H03K5/00 ,  H04L27/38

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.