公开(公告)号：US12255921B2

公开(公告)日：2025-03-18

申请号：US17349247

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Akhilesh S. Thyagaturu ,  Vinodh Gopal

IPC: H04L9/40

Abstract: Methods, apparatus, and software for efficient encryption in virtual private network (VPN) sessions. A VPN link and an auxiliary link (and associated sessions) are established between computing platforms to support end-to-end communication between respective application running on the platforms. The VPN link may employ a conventional VPN protocol such as TLS or IPsec, while the auxiliary link comprises a NULL encryption VPN tunnel. To transfer data, a determination is made to whether the data are encrypted or non-encrypted. Encrypted data are transferred over the auxiliary link to avoid re-encryption of the data. Non-encrypted are transferred over the VPN link. TLS and IPsec VPN agents may be used to assist in setting up the VPN and auxiliary sessions. The techniques avoid double encryption of VPN traffic, while ensuring that various types of traffic transferred between platforms is encrypted.

公开(公告)号：US12118130B2

公开(公告)日：2024-10-15

申请号：US17214820

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Vinodh Gopal

IPC: G06F21/72 ,  G06F21/64 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F21/64 ,  H04L9/0643

Abstract: Systems, methods, and apparatuses for low-latency page efficient chained decryption and decompression acceleration are described. In one embodiment, a processor comprises a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit to: in response to a descriptor, comprising an indication of a hash key and encrypted data to be decrypted, from the hardware processor core, perform a determination that the encrypted data is to be read in an encrypted order or a reverse order from the encrypted order, in response to the determination that the encrypted data is to be read in the reverse order, generate a resultant authentication tag in the reverse order for the encrypted data based at least in part on the hash key without reordering the encrypted data in the reverse order into the encrypted order, and, in response to the determination that the encrypted data is to be read in the encrypted order, generate the resultant authentication tag in the encrypted order for the encrypted data based at least in part on the hash key.

公开(公告)号：US11989582B2

公开(公告)日：2024-05-21

申请号：US17033760

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： James Guilford ,  George Powley ,  Vinodh Gopal ,  Wajdi Feghali

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/3887 ,  G06F2209/483

Abstract: Apparatus and method for performing low-latency multi-job submission via a single job descriptor is described herein. An apparatus embodiment includes a plurality of descriptor queues to stores job descriptors describing work to be performed and enqueue circuitry to receive a first job descriptor which includes a first field to store a Single Instruction Multiple Data (SIMD) width. If the SIMD width indicates that the first job descriptor is an SIMD job descriptor and open slots are available in the descriptor queues to store new job descriptors, then the enqueue circuitry is to generate a plurality of job descriptors based on fields of the first job descriptor and to store them in the open slots of the descriptor queues. The generated job descriptors are processed by processing pipelines to perform the work described. At least some of the generated job descriptors are processed concurrently or in parallel by different processing pipelines.

公开(公告)号：US11956156B2

公开(公告)日：2024-04-09

申请号：US17016555

申请日：2020-09-10

Applicant: Intel Corporation

Inventor： Akhilesh S. Thyagaturu ,  Vinodh Gopal

IPC: H04L47/2441 ,  H04L9/40 ,  H04L43/028 ,  H04L49/90

CPC classification number: H04L47/2441 ,  H04L43/028 ,  H04L49/9084 ,  H04L63/0245

Abstract: Methods and apparatus for dynamic offline end-to-end packet processing based on traffic class. An end-to-end connection is set up between an application on a client including a processor and host memory and an application on a remote server. An offline packet buffer is allocated in host memory. While the processor and/or a core on with the client application is executed is in a sleep state, the client is operated in an interrupt-less and polling-less mode as applied to a predetermined traffic class. Under the mode, a Network Interface Controller (NIC) at the client receives network traffic from the remote server and determines whether the network traffic is associated with the predetermined traffic class. When it is, the NIC writes packet data extracted from the network traffic to an offline packet buffer. Descriptors are generated and provided to the NIC to inform the NIC of the location and size of the offline packet buffer.

公开(公告)号：US20240113863A1

公开(公告)日：2024-04-04

申请号：US18129814

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Pablo De Lara Guarch ,  Tomasz Kantecki ,  Krystian Matusiewicz ,  Wajdi Feghali ,  Vinodh Gopal ,  James D. Guilford

IPC: H04L9/06 ,  H04L9/32 ,  H04W12/037

CPC classification number: H04L9/065 ,  H04L9/3215 ,  H04W12/037

Abstract: Methods and apparatus relating to an efficient implementation of ZUC authentication are described. In one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. The tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. Other embodiments are also claimed and disclosed.

公开(公告)号：US11909841B2

公开(公告)日：2024-02-20

申请号：US16887087

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Kenneth Shoemaker ,  Vinodh Gopal ,  Ned M. Smith

IPC: H04L29/08 ,  H04L67/56 ,  H04L49/00 ,  H04L47/80 ,  H04L49/90 ,  H04L49/109

CPC classification number: H04L67/56 ,  H04L47/805 ,  H04L49/109 ,  H04L49/3018 ,  H04L49/9068

Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.

公开(公告)号：US20240028577A1

公开(公告)日：2024-01-25

申请号：US18225939

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Jixing Gu ,  Vinodh Gopal ,  Fang Xie ,  David Cohen ,  Wajdi Feghali

IPC: G06F16/22

CPC classification number: G06F16/2272 ,  G06F16/24568

Abstract: An apparatus may include an accelerator and a processor. The processor may receive an input string targeting a data buffer comprising a plurality of strings. The processor may receive, from the accelerator, a fixed-length data buffer based on the data buffer, respective ones of a plurality of entries of the fixed-length data buffer based on respective ones of the strings. The processor may receive, from the accelerator, a plurality of streams, respective ones of the plurality of streams to comprise a portion of respective entries in the fixed-length data buffer. The processor may generate, based on the input string, a plurality of target portions of the input string. The processor may receive, from the accelerator, indexes of the plurality of streams based on respective target portions of the input string matching respective entries of the plurality of streams. The processor may aggregate the indexes received from the accelerator.

公开(公告)号：US11748103B2

公开(公告)日：2023-09-05

申请号：US17672253

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/3013 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20220353070A1

公开(公告)日：2022-11-03

申请号：US17718237

申请日：2022-04-11

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US11483009B2

公开(公告)日：2022-10-25

申请号：US16407105

申请日：2019-05-08

Applicant: Intel Corporation

Inventor： Vinodh Gopal

IPC: H03M7/30 ,  H03M7/40 ,  H04L1/00

Abstract: Methods, apparatus, systems, and software for implementing self-checking compression. A byte stream is encoded to generate tokens and selected tokens are encoded with hidden parity information in a compressed byte stream that may be stored for later streaming or streamed to a receiver. As the compressed byte stream is received, it is decompressed, with the hidden parity information being decoded and used to detect for errors in the decompressed data, enabling errors to be detected on-the-fly rather than waiting to perform a checksum over an entire received file. In one embodiment the byte stream is encoded using a Lempel-Ziv 77 (LZ77)-based encoding process to generate a sequence of tokens including literals and references, with all or selected references encoded with hidden parity information in a compressed byte stream having a standard format such as DEFLATE or Zstandard. The hidden parity information is encoded such that the compressed byte stream may be decompressed without parity checks using standard DEFLATE or Zstandard decompression schemes. Dictionary coders such as LZ78 and LZW may also be used.