公开(公告)号：US20200371786A1

公开(公告)日：2020-11-26

申请号：US16878608

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F7/53

Abstract: A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.

公开(公告)号：US20200319881A1

公开(公告)日：2020-10-08

申请号：US16852690

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US10732689B2

公开(公告)日：2020-08-04

申请号：US15638407

申请日：2017-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui

IPC: G06F1/3234 ,  G06F1/28 ,  G06F13/26 ,  G06F9/30 ,  G06F1/3287 ,  G06F1/3206 ,  G06F9/38

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

公开(公告)号：US10423413B2

公开(公告)日：2019-09-24

申请号：US14326943

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US10402199B2

公开(公告)日：2019-09-03

申请号：US14920298

申请日：2015-10-22

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: One embodiment of this invention provides two conditional execution auxiliary instructions directed to disparate subsets of the plural functional units. Depending on the conditional execution desired, only one of the two conditional execution auxiliary instructions may be required for a particular execute packet. Another embodiment of this invention employs only one of two possible register files for the condition registers. In a VLIW processor it may be advantageous to split the functional units into separate sets with corresponding register files. This limits the number of functional units that may simultaneously access the register files. In the preferred embodiment of this invention the functional units are divided into a scalar set which access scalar registers and a vector set which access vector registers. The data registers storing the conditions for both scalar and vector instructions are in the scalar data register file.

公开(公告)号：US20190020360A1

公开(公告)日：2019-01-17

申请号：US15651055

申请日：2017-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  H03M13/27

Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.

公开(公告)号：US20180253402A1

公开(公告)日：2018-09-06

申请号：US15907356

申请日：2018-02-28

Applicant: Texas Instruments Incorporated

Inventor： Arthur John Redfern ,  Timothy David Anderson ,  Kai Chirca ,  Chenchi Luo ,  Zhenhua Yu

IPC: G06F17/16 ,  G06F17/14

CPC classification number: G06F17/16 ,  G06F17/141 ,  G06N3/0454 ,  G06N3/063

Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

公开(公告)号：US10007518B2

公开(公告)日：2018-06-26

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

公开(公告)号：US20150019836A1

公开(公告)日：2015-01-15

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

Abstract translation: 所需的寄存器数量通过重叠标量和向量寄存器来减少。 这也允许在混合标量和向量指令时增加编译器的灵活性。 通过限制读取访问来使本地寄存器读取端口最小化。 专用谓词寄存器减少通用寄存器的要求，并允许通过允许将谓词寄存器放置在谓词单元旁边来减少关键定时路径。

公开(公告)号：US20250094359A1

公开(公告)日：2025-03-20

申请号：US18966268

申请日：2024-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.