公开(公告)号：US20230145872A1

公开(公告)日：2023-05-11

申请号：US18066141

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L29/0673 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/78684

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US20230122250A1

公开(公告)日：2023-04-20

申请号：US17737915

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Chih-Hao Wang ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234

Abstract: A device includes a substrate, first and second gate structures, first and second hybrid fins, and first and second sidewalls. The first gate structure is over and surrounds a first vertical stack of nanostructures. The second gate structure is over and surrounds a second vertical stack of nanostructures. The second gate structure and the first gate structure extend along a first direction, and are laterally separated from each other in a second direction, the second direction being substantially perpendicular to the first direction. The first hybrid fin extends through and under the first gate structure and the second gate structure, the extending being along the second direction. The second hybrid fin is between the first gate structure and the second gate structure. The second hybrid fin has: a first sidewall that abuts the first gate structure; and a second sidewall that abuts the second gate structure.

公开(公告)号：US11631749B2

公开(公告)日：2023-04-18

申请号：US17681588

申请日：2022-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/768

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a side of the dummy gate. The dummy gate is replaced with a gate structure, such that that first gate spacer is on a side of the gate structure. The gate structure is etched back. After etching back the gate structure, a top portion of the first gate spacer is removed. A second gate spacer is formed over a remaining portion of the first gate spacer. After forming the second gate spacer, a dielectric cap is formed over the gate structure.

公开(公告)号：US11631638B2

公开(公告)日：2023-04-18

申请号：US17582314

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more channel layers connecting the first and the second S/D features, a high-k metal gate engaging the one or more channel layers, an isolation structure, a power rail under the isolation structure, and a via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail. At least a portion of the isolation structure is under the first and the second S/D features. In a cross-section that extends through the first S/D feature and perpendicular to a direction from the first S/D feature to the second S/D feature along the one or more channel layers, the via structure extends into a gap vertically between the first S/D feature and the isolation structure.

公开(公告)号：US20230113266A1

公开(公告)日：2023-04-13

申请号：US18053236

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

公开(公告)号：US11621323B2

公开(公告)日：2023-04-04

申请号：US17135623

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

公开(公告)号：US11621195B2

公开(公告)日：2023-04-04

申请号：US16856033

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Yi-Bo Liao ,  Yi-Ruei Jhan

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

公开(公告)号：US11610977B2

公开(公告)日：2023-03-21

申请号：US16941504

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

公开(公告)号：US11588050B2

公开(公告)日：2023-02-21

申请号：US17112293

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

公开(公告)号：US11581436B2

公开(公告)日：2023-02-14

申请号：US17113821

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.