公开(公告)号：US11658220B2

公开(公告)日：2023-05-23

申请号：US17123873

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Kuo-Cheng Chiang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/4175 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The second source/drain epitaxial structure has a concave bottom surface.

公开(公告)号：US11616062B2

公开(公告)日：2023-03-28

申请号：US17170740

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Zhi-Chang Lin ,  Chih-Hao Wang ,  Shih-Cheng Chen

IPC: H01L29/423 ,  H01L21/763 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

公开(公告)号：US11610983B2

公开(公告)日：2023-03-21

申请号：US17189678

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a dielectric isolation structure disposed on the substrate, a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure, first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin, a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins, and an epitaxial feature over the semiconductor fin. The epitaxial feature has a bottom portion laterally between the first and second dielectric fins.

公开(公告)号：US11569234B2

公开(公告)日：2023-01-31

申请号：US17027322

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Yi-Ruei Jhan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

公开(公告)号：US11527533B2

公开(公告)日：2022-12-13

申请号：US16888457

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.

公开(公告)号：US20220375936A1

公开(公告)日：2022-11-24

申请号：US17873787

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/26

Abstract: A semiconductor device includes first and second n-type transistors and first and second p-type transistors. The first n-type transistor includes a first channel layer and a first portion of a high-k dielectric layer over the first channel layer. The second n-type transistor includes a second channel layer and a second portion of the high-k dielectric layer over the second channel layer, wherein the second portion includes a higher amount of an n-type dipole material than the first portion. The first p-type transistor includes a third channel layer and a third portion of the high-k dielectric layer over the third channel layer. The second p-type transistor includes a fourth channel layer and a fourth portion of the high-k dielectric layer over the fourth channel layer, wherein the fourth portion includes a higher amount of a p-type dipole material than the third portion.

公开(公告)号：US11502034B2

公开(公告)日：2022-11-15

申请号：US17027344

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lo-Heng Chang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238

Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

公开(公告)号：US20220344465A1

公开(公告)日：2022-10-27

申请号：US17566560

申请日：2021-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

公开(公告)号：US20220310826A1

公开(公告)日：2022-09-29

申请号：US17842193

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Ching-Wei Tsai ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L21/02 ,  H01L21/283 ,  H01L29/78

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

公开(公告)号：US20220293759A1

公开(公告)日：2022-09-15

申请号：US17199629

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.