公开(公告)号：US06872989B2

公开(公告)日：2005-03-29

申请号：US10370766

申请日：2003-02-24

Applicant: Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

Inventor： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/77 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L31/0312

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

Abstract: A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

Abstract translation: 在Si衬底101上依次沉积氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。将Si衬底101放置在室106中，以便将PZT膜105x照射 EHF波108.用EHF波的照射局部加热诸如PZT膜的电介质膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US06852602B2

公开(公告)日：2005-02-08

申请号：US10298000

申请日：2002-01-30

Applicant: Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

Inventor： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

IPC: H01L21/205 ,  H01L29/15 ,  H01L29/24 ,  H01L29/737 ,  H01L29/80 ,  H01L21/331

CPC classification number: H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/7378 ,  H01L29/802

Abstract: A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1 y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Abstract translation: 通过层叠具有小Ge摩尔分数的Si1-x1-y1Gex1Cy1层（0 <= x1 <1和0 y2），例如Si0.2Ge0.8层 以这种方式，多层膜用作结合到晶格点中的C原子的SiGeC层的范围延伸到Ge摩尔分数高的高度。

公开(公告)号：US20050017265A1

公开(公告)日：2005-01-27

申请号：US10913383

申请日：2004-08-09

Applicant: Takeshi Takagi ,  Akira Inoue

Inventor： Takeshi Takagi ,  Akira Inoue

IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/165 ,  H01L29/786 ,  H01L29/80 ,  H01L31/072 ,  H01L21/336

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/78687

Abstract: A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

Abstract translation: 位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。 处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。 位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。 位于栅极绝缘膜12正下方的Si膜18的区域是掺杂p型杂质（5×10 17原子％-3）的Si帽区24。 因此，可以实现抑制阈值电压增加的半导体装置。

公开(公告)号：US06828602B2

公开(公告)日：2004-12-07

申请号：US10031445

申请日：2002-01-22

Applicant: Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

Inventor： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

IPC: H01L31072

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/7378 ,  Y10S438/936

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract translation: 通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成第二沉积氧化物膜112，该第二沉积氧化物膜112具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，形成发射极扩散层153a 通过将磷扩散到Si覆盖层153中。当Si覆盖层153生长时，通过原位掺杂使Si覆盖层153仅在其上部包含硼，则耗尽层的宽度 154变窄，并且复合电流降低，从而可以提高电流特性的线性。

公开(公告)号：US06815735B2

公开(公告)日：2004-11-09

申请号：US10311267

申请日：2002-12-13

Applicant: Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

Inventor： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC: H01L310328

CPC classification number: H01L29/78696 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/783 ,  H01L29/78606 ,  H01L29/78687 ,  H01L29/802

Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.

Abstract translation: 梯度SiGe-HDTMOS的半导体层30由上部Si膜12，Si缓冲层13，Si1-xGex膜14和Si覆盖层15构成。源区域20a和漏极区域20b之间的区域 半导体层30包括高浓度n型Si体区域22和n Si区域23，Si帽区域25和SiGe沟道区域24.使Si1-xGex膜14的Ge组成比x增加 从Si缓冲层13到Si覆盖层15.对于p型HDTMOS，衬底电流的电子电流分量降低。

公开(公告)号：US06759697B2

公开(公告)日：2004-07-06

申请号：US10461364

申请日：2003-06-16

Applicant: Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

Inventor： Kenji Toyoda ,  Koichiro Yuki ,  Takeshi Takagi ,  Teruhito Ohnishi ,  Minoru Kubo

IPC: H01L29737

CPC classification number: H01L29/7378

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

公开(公告)号：US06472685B2

公开(公告)日：2002-10-29

申请号：US09203098

申请日：1998-12-02

Applicant: Takeshi Takagi

Inventor： Takeshi Takagi

IPC: H01L310312

CPC classification number: H01L29/7786 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7782 ,  H01L29/802

Abstract: A first silicon layer (Si layer), a second silicon layer (Si1Cy layer) containing carbon and a third silicon layer not containing carbon are stacked in this order on a silicon substrate. Since the lattice constant of the Si1-yCy layer is smaller than that of the Si layer, the conduction band and the valence band of the second silicon layer receive a tensile strain to be split. Electrons having a smaller effective mass, which have been induced by an electric field applied to a gate electrode, are confined in the second silicon layer, and move in the channel direction. Thus, an n-MOSFET having extremely high mobility can be obtained. Furthermore, if the second silicon layer is made of Sil-x-yGexCy, a structure suitable for a high-performance CMOS device can be formed. A high-performance field effect transistor can be provided at lower costs by using a heterojunction structure mainly composed of silicon.

Abstract translation: 将含有碳的第一硅层（Si层），第二硅层（Si1Cy层）和不含碳的第三硅层依次层叠在硅基板上。 由于Si1-yCy层的晶格常数小于Si层的晶格常数，所以第二硅层的导带和价带受到分裂的拉伸应变。 具有由施加到栅电极的电场感应的有效质量较小的电子被限制在第二硅层中，并且在沟道方向上移动。 因此，可以获得具有极高迁移率的n-MOSFET。 此外，如果第二硅层由Sil-x-yGexCy制成，则可以形成适用于高性能CMOS器件的结构。 通过使用主要由硅组成的异质结结构，可以以更低的成本提供高性能场效应晶体管。

公开(公告)号：US06455364B1

公开(公告)日：2002-09-24

申请号：US09526686

申请日：2000-03-15

Applicant: Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

Inventor： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC: H01L218249

CPC classification number: H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

Abstract translation: 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US5972425A

公开(公告)日：1999-10-26

申请号：US8247

申请日：1998-01-16

Applicant: Tadahiko Nishi ,  Takeshi Takagi ,  Yoshitaka Okude

Inventor： Tadahiko Nishi ,  Takeshi Takagi ,  Yoshitaka Okude

IPC: B05D7/00 ,  C08G81/02 ,  B05D3/02

CPC classification number: B05D7/57 ,  B05D7/577 ,  C08G81/027 ,  Y10S525/902 ,  Y10T428/31692

Abstract: A heat-curable, water-dispersible resin composition comprising 50 to 90% by weight of a film-forming polymer (A) obtained by copolymerizing an ethylenic monomer having a saturated C.sub.6 to C.sub.18 hydrocarbon group, a hydroxy-containing ethylenic monomer, an acidic group-containing ethylenic monomer and another ethylenic monomer, and 50 to 10% by weight of a hydroxy-terminated polyester resin (B), said resin (B) being grafted on said polymer (A) by transesterification, and at least part of the acidic groups in said polymer (A) being neutralized with a base (C); a method of producing said resin composition; a water-based paint composition comprising said resin composition and a curing agent; and a two-coat one-bake coating method which uses said paint composition as a base coat. This invention provides a water-based paint composition which shows good workability in a broad humidity condition range, and excellent in storage stability, paint film appearance and performance characteristics.

Abstract translation: 一种可热固化的水分散性树脂组合物，其包含50-90重量％的通过共聚具有饱和C6至C18烃基的烯属单体，含羟基的乙烯性单体，酸性 含有乙烯基的单体和另一种乙烯性单体，和50〜10重量％的羟基封端的聚酯树脂（B），所述树脂（B）通过酯交换接枝在所述聚合物（A）上，并且至少部分 所述聚合物（A）中的酸性基团用碱（C）中和; 一种生产所述树脂组合物的方法; 包含所述树脂组合物和固化剂的水性涂料组合物; 和使用所述涂料组合物作为底涂层的双层单烘烤涂布法。 本发明提供了一种水溶性涂料组合物，其在宽湿度条件范围内表现出良好的加工性，并且储存稳定性，漆膜外观和性能特性优异。

公开(公告)号：US5919856A

公开(公告)日：1999-07-06

申请号：US993410

申请日：1997-12-18

Applicant: Tadahiko Nishi ,  Takeshi Takagi ,  Yoshitaka Okude

Inventor： Tadahiko Nishi ,  Takeshi Takagi ,  Yoshitaka Okude

IPC: B05D1/36 ,  B05D7/24 ,  C08G12/32 ,  C08G18/80 ,  C08G63/49 ,  C08G63/52 ,  C08G63/60 ,  C09D167/00 ,  C09D167/08 ,  C08J3/00 ,  B05D3/02 ,  C08K3/20 ,  C08L51/00

CPC classification number: C09D167/00

Abstract: A water-based thermosetting coating composition comprises a polyester resin having a number of pendant carboxyl groups and a crosslinker for the resin both dispersed in an aqueous medium containing a neutralizing base. The polyester resin contains as polyester-forming polyhydric alcohol reactants from 1 to 40% by weight of the entire polyester-forming reactants of a polyalkadienediol or a hydrogenated products thereof and from 2 to 50% by weight of the entire polyester-forming reactants of a 2,2-bis(hydroxymethyl)alkanoic acid. The coating composition is useful for forming a multilayer coating film on metallic substrates such as automobile bodies by applying the coating composition as an intermediate coating layer between an electrodeposition coating layer and a top coating layer.

Abstract translation: 水性热固性涂料组合物包含具有多个侧链羧基的聚酯树脂和用于树脂的交联剂，其分散在含有中和碱的水性介质中。 聚酯树脂含有作为聚酯形成多元醇的反应物，其为聚亚烷基二醇或其氢化产物的整个聚酯形成反应物的1-40重量％和2-50重量％的整个聚酯形成反应物 2,2-双（羟甲基）链烷酸。 该涂料组合物可用于通过在电沉积涂层和顶涂层之间涂覆涂料组合物作为中间涂层，在诸如汽车车身的金属基材上形成多层涂膜。