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公开(公告)号：US11128388B2
公开(公告)日：2021-09-21
申请号：US16582448
申请日：2019-09-25
Applicant: Rambus Inc.
Inventor： Jun Kim , Wayne S. Richardson , Glenn Chiu
Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
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公开(公告)号：US11121893B2
公开(公告)日：2021-09-14
申请号：US16685886
申请日：2019-11-15
Applicant: Rambus Inc.
Inventor： John Wood Poulton
Abstract: A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.
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公开(公告)号：US20210279191A1
公开(公告)日：2021-09-09
申请号：US17191469
申请日：2021-03-03
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Thomas J. Giovannini
Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.
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公开(公告)号：US20210271301A1
公开(公告)日：2021-09-02
申请号：US17141102
申请日：2021-01-04
Applicant: Rambus Inc.
Inventor： Stephen G. Tell
Abstract: A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.
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公开(公告)号：US11108510B2
公开(公告)日：2021-08-31
申请号：US16861164
申请日：2020-04-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Richard E. Perego , Craig E. Hampel
IPC: H04L7/00 , H04L1/24 , H04L7/10 , H04L25/02 , H04L25/12 , G11C29/02 , G11C7/10 , H04L27/00 , G11C7/04 , H04L7/033
Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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Patent Agency Ranking
公开(公告)号：US11101393B2
公开(公告)日：2021-08-24
申请号：US16673431
申请日：2019-11-04
Applicant: Rambus Inc.
Inventor： Yohan Frans , Simon Li , John Eric Linstadt , Jun Kim
IPC: H01L31/0236 , G06F3/06 , G06F13/372 , G06F13/16 , G06F12/02 , G06F12/00
Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
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公开(公告)号：US20210250038A1
公开(公告)日：2021-08-12
申请号：US17166919
申请日：2021-02-03
Applicant: Rambus Inc.
Inventor： Shankar Tangirala
Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
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公开(公告)号：US20210241822A1
公开(公告)日：2021-08-05
申请号：US16973241
申请日：2019-05-25
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang
IPC: G11C11/406
Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.
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公开(公告)号：US11082268B2
公开(公告)日：2021-08-03
申请号：US17065043
申请日：2020-10-07
Applicant: Rambus Inc.
Inventor： Robert E. Palmer
Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
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公开(公告)号：US20210232507A1
公开(公告)日：2021-07-29
申请号：US17107831
申请日：2020-11-30
Applicant: Rambus Inc.
Inventor： Trung Diep , Hongzhong Zheng
IPC: G06F12/1009 , G06F12/0864 , G06F12/0811 , G11C7/10
Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.
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