公开(公告)号：US20220077327A1

公开(公告)日：2022-03-10

申请号：US17445371

申请日：2021-08-18

申请人： Rambus Inc.

发明人： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC分类号： H01L31/0236 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372

摘要： A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US09230609B2

公开(公告)日：2016-01-05

申请号：US13908973

申请日：2013-06-03

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L25/065

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/22 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

摘要翻译： 封装的半导体器件包括数据引脚，第一存储器管芯和与第一存储器管芯堆叠的第二存储器管芯。 第一存储器管芯包括耦合到数据引脚的第一数据接口和具有多个存储体的第一存储器核心。 第二存储器管芯包括具有多个堤的第二存储器芯。 响应于第一命令信号和第二命令信号的并行列访问操作，第一存储器核心的相应组和第二存储器核心的相应组执行并行行存取操作。 第一管芯的第一数据接口将第一和第二管芯中的并行列访问操作的聚合数据提供给数据引脚。

公开(公告)号：US20200176617A1

公开(公告)日：2020-06-04

申请号：US16673431

申请日：2019-11-04

申请人： Rambus Inc.

发明人： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC分类号： H01L31/0236 ,  G06F13/372 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

摘要： A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US10453500B2

公开(公告)日：2019-10-22

申请号：US15907212

申请日：2018-02-27

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  H01L25/065

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US12131796B2

公开(公告)日：2024-10-29

申请号：US18195860

申请日：2023-05-10

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US20130336039A1

公开(公告)日：2013-12-19

申请号：US13908973

申请日：2013-06-03

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  G11C7/22 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

摘要翻译： 封装的半导体器件包括数据引脚，第一存储器管芯和与第一存储器管芯堆叠的第二存储器管芯。 第一存储器管芯包括耦合到数据引脚的第一数据接口和具有多个存储体的第一存储器核心。 第二存储器管芯包括具有多个堤的第二存储器芯。 响应于第一命令信号和第二命令信号的并行列访问操作，第一存储器核心的相应组和第二存储器核心的相应组执行并行行存取操作。 第一管芯的第一数据接口将第一和第二管芯中的并行列访问操作的聚合数据提供给数据引脚。

公开(公告)号：US11973153B2

公开(公告)日：2024-04-30

申请号：US17445371

申请日：2021-08-18

申请人： Rambus Inc.

发明人： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC分类号： H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC分类号： H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

摘要： A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20230395103A1

公开(公告)日：2023-12-07

申请号：US18195860

申请日：2023-05-10

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US20210217448A1

公开(公告)日：2021-07-15

申请号：US17135174

申请日：2020-12-28

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US10885949B2

公开(公告)日：2021-01-05

申请号：US16653252

申请日：2019-10-15

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  H01L25/065

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.