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221.发明申请公开(公告)号：US20180323871A1
公开(公告)日：2018-11-08
申请号：US16024105
申请日：2018-06-29
Applicant: INPHI CORPORATION
Inventor： Shu Hao FAN , Damian Alfonso MORERO , Mario Rafael HUEDA
IPC: H04B10/079 , H04L25/03 , H04B10/40 , H04B10/50 , H04B10/61
CPC classification number: H04B10/07955 , H04B7/005 , H04B7/0413 , H04B10/40 , H04B10/5053 , H04B10/5161 , H04B10/532 , H04B10/61 , H04B10/616 , H04L25/03 , H04L25/14
Abstract: Apparatus and method for transmitter alignment in an optical communication system are provided. In certain configurations, a method of correcting for transmitter skew is provided. The method includes generating an optical signal using a transmitter based on an in-phase (I) component and a quadrature-phase (Q) component of a transmit signal, the optical signal having a baud rate that is based on a timing tone. The method further includes receiving the optical signal as an input to a receiver, and generating a signal vector representing the optical signal using the receiver. The signal vector includes an I component and a Q component. The method further includes calculating a power of the timing tone based on processing the signal vector using a tone power calculator of the receiver, and correcting for a skew of the transmitter based on the calculated power.
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公开(公告)号：US20180323577A1
公开(公告)日：2018-11-08
申请号：US16039568
申请日：2018-07-19
Applicant: INPHI CORPORATION
Inventor： Brian TAYLOR , Radhakrishnan L. NAGARAJAN , Masaki KATO
CPC classification number: H01S5/0687 , G02B6/125 , G02B6/2813 , G02B6/2861 , G02B6/4286 , G02B2006/12135 , G02B2006/1215 , H01S5/12 , H04B10/5057 , H04J14/02
Abstract: A wavelength locker integrated with a silicon photonics transmission system comprising a silicon-on-insulator (SOI) substrate and an input via a power tap coupler to receive a fraction of a transmission signal with one or more frequencies from a primary output path of the silicon photonics transmission system. The wavelength locker further includes a splitter configured to split the input to a first signal in a first path and a second signal in a second path and a first delay-line-interferometer (DLI) coupled to the second path to receive the second signal and configured to generate an interference spectrum and output at least two sub-spectrums tunable to keep quadrature points of the sub-spectrums at respective one or more target frequencies. The wavelength locker is configured to generate an error signal fed back to the silicon photonics transmission system for locking the one or more frequencies at the one or more target frequencies.
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公开(公告)号：US10122368B2
公开(公告)日：2018-11-06
申请号：US15840984
申请日：2017-12-13
Applicant: INPHI CORPORATION
Inventor： Simon Forey , Rajasekhar Nagulapalli , Parmanand Mishra
Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
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公开(公告)号：US10122335B2
公开(公告)日：2018-11-06
申请号：US15811036
申请日：2017-11-13
Applicant: INPHI CORPORATION
Inventor： Rajasekhar Nagulapalli , Simon Forey , Parmanand Mishra
Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.
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225.发明授权公开(公告)号：US10122056B2
公开(公告)日：2018-11-06
申请号：US15639013
申请日：2017-06-30
Applicant: INPHI CORPORATION
Abstract: A circuit for blocking undesired input direct current of AC-coupled broadband circuits. The circuit includes a capacitor coupled to an input port and a common node. The input port receives a RF input signal. Additionally, the circuit includes a current source supplying a DC current to the common node leading a bias current to an output port. Further, the circuit includes a variable voltage source through an internal load and a close loop with an application circuit having an input load coupled to the output port to determine various bias voltages to control the bias current at the output port in association with a RF output signal that is substantially free of any input direct current originated from the RF input signal and is associated with an inherent low cut-off frequency independent of the various bias voltages.
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Patent Agency Ranking
公开(公告)号：US10116393B2
公开(公告)日：2018-10-30
申请号：US15976659
申请日：2018-05-10
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. Nagarajan , Todd Rope
Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.
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公开(公告)号：US20180309520A1
公开(公告)日：2018-10-25
申请号：US16022573
申请日：2018-06-28
Applicant: INPHI CORPORATION
Inventor： Shu Hao FAN
CPC classification number: H04B10/40 , H04B10/5057 , H04B10/613 , H04B10/6165 , H04B2210/252
Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.
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228.发明授权公开(公告)号：US10110317B1
公开(公告)日：2018-10-23
申请号：US15256210
申请日：2016-09-02
Applicant: INPHI CORPORATION
Inventor： Damian Alfonso Morero , Mario Rafael Hueda , Shu Hao Fan
IPC: H04B10/06 , H04B10/61 , H04B10/516 , H04L25/03 , H04B7/005 , H04B7/0413
Abstract: Apparatus and method for compensating for transmitter errors in an optical communication system are provided. In certain configurations herein, a receiver is provided for processing an analog signal vector representing an optical signal received from a transmitter. The receiver includes an analog front-end that converts the analog signal vector into a digital signal vector including a digital representation of an I component and a Q component of the optical signal. The receiver further includes a digital signal processing circuit configured to process the digital signal vector to recover data, and the digital signal processing circuit includes a transmitter error compensation system that compensates the digital signal vector for at least one of a transmit skew error of the transmitter or a modulator biasing error of the transmitter.
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公开(公告)号：US20180302108A1
公开(公告)日：2018-10-18
申请号：US16011483
申请日：2018-06-18
Applicant: INPHI CORPORATION
Inventor： Benjamin SMITH , Arash FARHOODFAR , Stewart CROZIER , Frank R. KSCHISCHANG , Andrew HUNT
CPC classification number: H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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公开(公告)号：US20180287577A1
公开(公告)日：2018-10-04
申请号：US15995008
申请日：2018-05-31
Applicant: INPHI CORPORATION
Inventor： James GORECKI
CPC classification number: H03G1/007 , H03F1/0205 , H03F1/56 , H03F3/45197 , H03F2203/45492 , H03G3/001
Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.
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