公开(公告)号：US09326234B2

公开(公告)日：2016-04-26

申请号：US13710282

申请日：2012-12-10

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02 ,  H04W52/14

CPC classification number: H04W52/0206 ,  H04W52/0219 ,  Y02D70/142

Abstract: Methods and systems are disclosed for reduced power consumption in communication networks, including sensor networks implemented according to IEEE 802.11ah, by organizing stations into groups having long sleep periods. By organizing the stations of the network into groups, the access point can match each group's traffic identification map with its target beacon transmit time. One embodiment organizes the stations sequentially by AID numbers. Other embodiments organize the stations by similar power save requirements and/or nearby geographical location. Forms of an Extended Traffic Identification Map are matched with an awaken Target Beacon Transmit Time of the group.

Abstract translation: 公开的方法和系统通过将站组织成具有长睡眠周期的群组来降低通信网络中的功耗，包括根据IEEE 802.11ah实现的传感器网络。 通过将网络组合成组，接入点可以将每个组的流量识别图与其目标信标发送时间相匹配。 一个实施例按照AID号顺序组织站。 其他实施例通过类似的省电要求和/或附近的地理位置组织站。 扩展流量识别图的形式与组的唤醒目标信标发送时间相匹配。

公开(公告)号：US20160112598A1

公开(公告)日：2016-04-21

申请号：US14982335

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Francis C. STAFFORD

IPC: H04N1/195 ,  H04N1/60 ,  H04N1/10

CPC classification number: H04N1/19594 ,  H04N1/00827 ,  H04N1/10 ,  H04N1/46 ,  H04N1/60 ,  H04N2201/0081 ,  H04N2201/0084

Abstract: A method and apparatus for acquiring a corrected digital image of an object includes a digital camera operable to capture a plurality of color component images, an imager body and a support arm. The support arm is coupled to the imager body and adapted to support the digital camera. An image processor is provided to produce corrected color component images and an image combiner is provided to combine the corrected color component images to form the corrected digital image. The camera is moveable to more than one position to enable to formation of three-dimensional images or images with increased depth of focus.

Abstract translation: 用于获取对象的校正数字图像的方法和装置包括可操作以捕获多个颜色分量图像的数字照相机，成像器主体和支撑臂。 支撑臂联接到成像器主体并且适于支撑数字照相机。 提供图像处理器以产生校正的颜色分量图像，并且提供图像组合器以组合校正的颜色分量图像以形成校正的数字图像。 相机可以移动到多于一个位置，以使得能够形成具有增加的焦深的三维图像或图像。

公开(公告)号：US20160107444A1

公开(公告)日：2016-04-21

申请号：US14984672

申请日：2015-12-30

Applicant: STMICROELECTRONICS, INC.

Inventor： MURRAY J. ROBINSON ,  KENNETH J. STEWART

IPC: B41J2/14

CPC classification number: B41J2/1433 ,  B41J2/0458 ,  B41J2/14024 ,  B41J2/1404 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629

Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.

Abstract translation: 制造喷墨打印头的方法可以包括在第一晶片的第一表面中形成凹部以限定喷墨室。 该方法还可以包括形成从第一晶片的第二表面延伸到相应的喷墨室以形成喷墨孔的开口。 该方法还可以包括形成包括墨加热器的第二晶片，并将第一和第二晶片接合在一起，使得墨加热器在各个喷墨室内对齐，从而限定喷墨打印头。

公开(公告)号：US20160099923A1

公开(公告)日：2016-04-07

申请号：US14870872

申请日：2015-09-30

Applicant: STMicroelectronics, Inc.

Inventor： Prasad Golla ,  Francesco Varone

IPC: H04L29/06 ,  H04L9/32 ,  H04W12/04

CPC classification number: H04L63/061 ,  G06F21/53 ,  H04L9/3234 ,  H04L63/0492 ,  H04L63/0853 ,  H04L63/168 ,  H04W12/04 ,  H04W12/08

Abstract: A security module has an assigned unique electronic identifier. The security module has a communication interface, a non-volatile memory, and a processing unit coupled to the communication interface and the non-volatile memory. One or more unassigned secure domains are formed in the non-volatile memory, and each of the unassigned secure domains has an assigned unique application identifier (AID). Each of the unassigned secure domains is accessible via a respective first security value, and using the respective first security value, each of the unassigned secure domains can be assigned to a service provider before or after the security module is deployed.

Abstract translation: 安全模块具有分配的唯一电子标识符。 安全模块具有通信接口，非易失性存储器和耦合到通信接口和非易失性存储器的处理单元。 在非易失性存储器中形成一个或多个未分配的安全域，并且每个未分配的安全域具有分配的唯一应用标识符（AID）。 每个未分配的安全域可通过相应的第一安全值访问，并且使用相应的第一安全值，每个未分配的安全域可以在部署安全模块之前或之后分配给服务提供商。

公开(公告)号：US09299721B2

公开(公告)日：2016-03-29

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L21/30 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。

公开(公告)号：US09263338B2

公开(公告)日：2016-02-16

申请号：US14060874

申请日：2013-10-23

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US09245953B2

公开(公告)日：2016-01-26

申请号：US14597457

申请日：2015-01-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L21/8238 ,  H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US09240454B1

公开(公告)日：2016-01-19

申请号：US14520781

申请日：2014-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/00 ,  H01L21/82 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US20160014845A1

公开(公告)日：2016-01-14

申请号：US14856473

申请日：2015-09-16

Applicant: SMICROELECTRONICS ASIA PACIFIC PTE LTD ,  STMICROELECTRONICS, INC.

Inventor： Fuchao WANG ,  Olivier LE NEEL ,  Ravi SHANKAR

IPC: H05B3/00 ,  H05B3/06 ,  H01L23/34 ,  H05B3/34

CPC classification number: H05B3/0014 ,  H01L23/34 ,  H01L23/345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05B1/0227 ,  H05B3/02 ,  H05B3/06 ,  H05B3/12 ,  H05B3/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

公开(公告)号：US20160013206A1

公开(公告)日：2016-01-14

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract translation: 一种集成电路，包括：UTBOX层; 第一个电池，包括：FDSOI晶体管; 分离晶体管的第一STI; 位于一个晶体管下方并位于UTBOX层之下的第一接地平面; 第一口井 第二个电池，包括：FDSOI晶体管; 分离晶体管的第二STI; 位于一个晶体管下方并位于UTBOX层之下的第二接地平面; 第二口井 分离细胞的第三STI，到达第一和第二孔的底部; 连续地在第一和第二阱下方延伸的深阱，具有在第三STI下面的部分，其掺杂密度比第一和第二STI下面的深井的掺杂密度高至少50％。