公开(公告)号：US11626799B2

公开(公告)日：2023-04-11

申请号：US17393243

申请日：2021-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Bertolini ,  Alberto Cattani ,  Stefano Ramorini ,  Alessandro Gasparini

IPC: H02M3/158 ,  H02M1/00

Abstract: A converter circuit includes first and second electronic switches coupled at an intermediate node, with an inductor coupled between the intermediate node and an output node. Switching drive control circuitry causes the first and the second electronic switch to switch between a conductive state and a non-conductive state. The drive control circuitry includes a first feedback signal path to control switching of the first and the second electronic switch as a function of the difference between a feedback signal indicative of the signal at the output node and a reference value. A second feedback signal path includes a low-pass filter coupled to the output node and configured to provide a low-pass filtered feedback signal resulting from low-pass filtering of the output signal. The second feedback signal path compensates the feedback signal as a function of the difference between the low-pass filtered feedback signal and a respective reference value.

公开(公告)号：US11626355B2

公开(公告)日：2023-04-11

申请号：US17470269

申请日：2021-09-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

公开(公告)号：US20230103191A1

公开(公告)日：2023-03-30

申请号：US17947703

申请日：2022-09-19

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ignazio BERTUGLIA ,  Ettore CHIACCHIO

IPC: H01L29/872 ,  H01L29/739 ,  H01L29/06 ,  H02M7/537 ,  H01L21/265

Abstract: A RC-IGBT with fast recovery integrated diode is proposed adopting the concept of a hybrid structure with conventional IGBT emitter trench-stop, separated from an embedded low efficiency injection anode diode. The body region of the IGBT and the anode region of the diode are separately patterned and doped, and the metal barrier layer is removed from the diode area allowing a direct ohmic contact of AlSi alloy on the underneath P-doped anode. A full-anode contact opening is present in the diode area. Moreover, corresponding dummy trenches in the diode area are short-circuited to the emitter electrode giving the benefit to reduce the transfer Miller capacitance. In this way, a good trade-off of VF vs Err can be obtained for the integrated diode without downgrading the IGBT performances both in terms of VCEsat and leakage, differently from the case of devices manufactured by lifetime control techniques.

公开(公告)号：US20230098059A1

公开(公告)日：2023-03-30

申请号：US17487966

申请日：2021-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Claudio Adragna ,  Giovanni Gritti

IPC: H05B45/375

Abstract: In an embodiment, a control circuit includes: an output terminal configured to be coupled to a control terminal of a transistor that is coupled to an inductor; a logic circuit configured to control the transistor using a first signal; a zero crossing detection circuit configured to generate a freewheeling signal indicative of a demagnetization of the inductor; a comparator having first and second inputs configured to receive a sense voltage indicative of a current flowing through the transistor and a reference voltage, respectively, and an output configured to cause the logic circuit to dessert the first signal; and a reference generator configured to generate the reference voltage and including: a current generator, a capacitor and a resistor coupled to the output of the reference generator, and a switch coupled in series with the resistor and configured to be controlled based on the first signal and the freewheeling signal.

公开(公告)号：US20230096480A1

公开(公告)日：2023-03-30

申请号：US17488056

申请日：2021-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo CREMA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.

公开(公告)号：US20230096383A1

公开(公告)日：2023-03-30

申请号：US17951703

申请日：2022-09-23

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Claudio ADRAGNA ,  Massimiliano GOBBI ,  Giuseppe BOSISIO

IPC: H02M3/335

Abstract: An active flyback converter is transitioned between a plurality of operational states based on a comparison of a control voltage signal to voltage thresholds and a count of a number of consecutive switching cycles during which a clamp switch is kept off. The plurality of operational states includes a run state, an idle state, a first burst state, and a second burst state. Each set of consecutive switching cycles of the first burst state includes a determined number of switching cycles during which signals are generated to turn the power switch on and off and to maintain an off state of the clamp switch, and a switching cycle in a determined position in the set of switching cycles during which signals are sequentially generated to turn the power switch on, turn the power switch off, turn the clamp switch on and turn the clamp switch off.

公开(公告)号：US20230092543A1

公开(公告)日：2023-03-23

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20230090664A1

公开(公告)日：2023-03-23

申请号：US17946298

申请日：2022-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Riccardo CONDORELLI

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/60

Abstract: The present disclosure relates to a method including executing, by an electronic device, a first firmware module stored in a volatile memory of the electronic device, the execution of the first firmware module causing an updated firmware key to be stored in a non-volatile memory of the electronic device, and uploading a second firmware module to the electronic device. The method also includes decrypting the second firmware module by a cryptographic processor of the electronic device based on the updated firmware key, and installing the decrypted second firmware module in the volatile memory of the electronic device at least partially overwriting the first firmware module.

公开(公告)号：US20230087112A1

公开(公告)日：2023-03-23

申请号：US17939842

申请日：2022-09-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Filippo GIANNAZZO ,  Giuseppe Greco ,  Fabrizio ROCCAFORTE ,  Simone RASCUNA'

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/45 ,  H01L29/868 ,  H01L29/872 ,  H01L21/04

Abstract: Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.

公开(公告)号：US11610880B2

公开(公告)日：2023-03-21

申请号：US17182773

申请日：2021-02-23

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Giuseppe Patti

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.