公开(公告)号：US20230005902A1

公开(公告)日：2023-01-05

申请号：US17364377

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L27/108 ,  H01L25/00 ,  H01L23/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20230005854A1

公开(公告)日：2023-01-05

申请号：US17364335

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Beau D. Barry

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  G11C11/408 ,  G11C11/4091

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20230005816A1

公开(公告)日：2023-01-05

申请号：US17364292

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L27/108

Abstract: A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region comprising memory cells, each of the memory cells comprising an access device and a charge storage device operably coupled to the access device. The first microelectronic device structure further comprises a first base structure comprising first control logic devices configured to effectuate one or more control operations of the memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region comprising additional memory cells, each of the additional memory cells comprising an additional access device and an additional charge storage device operably coupled to the additional access device. The second microelectronic device further a second base structure comprising second control logic devices configured to effectuate one or more control operations of the additional memory cells of the second memory array region. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220216219A1

公开(公告)日：2022-07-07

申请号：US17141873

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Fatma Arzum Simsek-Ege

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a CMOS-containing base containing wordline-driver-circuitry. The wordline-driver-circuitry is subdivided amongst horizontally-extending sub-wordline-driver (SWD) units. Memory cells are over the base, and are arranged in vertically-extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Wordlines extend vertically along the rows. Each of the SWD units is associated with at least two of the wordlines and is configured to simultaneously activate the associated wordlines.

公开(公告)号：US11323521B1

公开(公告)日：2022-05-03

申请号：US17225204

申请日：2021-04-08

Applicant: Micron Technology, Inc.

Inventor： Sharmila Velamur ,  Fatma Arzum Simsek-Ege ,  Shivani Srivastava ,  Marsela Pontoh ,  Lavanya Sriram

IPC: G06F15/16 ,  H04L67/125 ,  H04L67/00

Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

公开(公告)号：US20220075369A1

公开(公告)日：2022-03-10

申请号：US17013185

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Deepti Verma ,  Anshika Sharma ,  Lavanya Sriram ,  Trupti D. Gawai

IPC: G05D1/00 ,  G05B13/02 ,  G07C5/00 ,  G07C5/08

Abstract: Apparatuses, and methods related machine learning (ML) with sensor information relevant to a location of a roadway are described. Memory systems including processing resource and memory resources receive sensor information from a sensor associated with a vehicle and a relevant to a location on a roadway. The received sensor information from the vehicle can be operated upon, using a ML algorithm, and an instruction can be transmitted based on ML algorithm. In an example, a method can include receiving, at a processing resource, sensor information from a sensor associated with a first vehicle and relevant to a location on a roadway, operating on the received sensor information associated with the first vehicle using a ML algorithm stored in a memory resource accessible by the processing resource, transmitting instructions relevant to the location, based on the sensor information associated with the first vehicle that was operated upon by the ML algorithm.

公开(公告)号：US20220036927A1

公开(公告)日：2022-02-03

申请号：US17501940

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey

IPC: G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210335815A1

公开(公告)日：2021-10-28

申请号：US17366471

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/11582 ,  H01L29/16 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/04 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8239 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11551

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US11063059B2

公开(公告)日：2021-07-13

申请号：US16052123

申请日：2018-08-01

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/115 ,  H01L29/788 ,  H01L27/11582 ,  H01L21/8239 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/792 ,  H01L27/11551

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US11043534B2

公开(公告)日：2021-06-22

申请号：US16735154

申请日：2020-01-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11553 ,  H01L27/1158 ,  H01L45/00

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.