公开(公告)号：US11889693B2

公开(公告)日：2024-01-30

申请号：US17366471

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H10B43/27 ,  H10B41/27 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L21/3213 ,  H10B99/00 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/792 ,  H10B41/20

CPC classification number: H10B43/27 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32134 ,  H01L29/04 ,  H01L29/16 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H10B41/27 ,  H10B99/00 ,  H01L29/7926 ,  H10B41/20

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US10170639B2

公开(公告)日：2019-01-01

申请号：US14987147

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11556 ,  H01L29/40 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11524 ,  H01L29/78

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

公开(公告)号：US10170491B2

公开(公告)日：2019-01-01

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11524

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US20170133392A1

公开(公告)日：2017-05-11

申请号：US15410469

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US20190214399A1

公开(公告)日：2019-07-11

申请号：US16237287

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

公开(公告)号：US20150287734A1

公开(公告)日：2015-10-08

申请号：US14746515

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

公开(公告)号：US20150140797A1

公开(公告)日：2015-05-21

申请号：US14610755

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US08946807B2

公开(公告)日：2015-02-03

申请号：US13748747

申请日：2013-01-24

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US20140264542A1

公开(公告)日：2014-09-18

申请号：US13864794

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

公开(公告)号：US20210335815A1

公开(公告)日：2021-10-28

申请号：US17366471

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/11582 ,  H01L29/16 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/04 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8239 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11551

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.