公开(公告)号：US20050166105A1

公开(公告)日：2005-07-28

申请号：US11015748

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/318563

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Abstract translation: 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试信号; 以及在所述至少一个测试输入和所述测试控制电路之间的多路复用器，所述多路复用器具有至少一个控制输入，由此所述多路复用器被控制以将测试信号引导到所述多个部分中的一个。

公开(公告)号：US20050132141A1

公开(公告)日：2005-06-16

申请号：US11046580

申请日：2005-01-28

Applicant: Andrew Sturges ,  David May

Inventor： Andrew Sturges ,  David May

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract translation: 提供一种缓存系统，其包括高速缓冲存储器和高速缓冲存储器补充机制，其根据主存储器中的项目的地址将高速缓冲存储器中的一组高速缓存分区中的一个或多个分配给项目。 这在所描述的实施例之一中通过用项目的地址包括一组分区选择器位来实现，所述分组选择器位允许生成分区掩码以识别可以加载该物品的高速缓存分区。

公开(公告)号：US20050066354A1

公开(公告)日：2005-03-24

申请号：US10917253

申请日：2004-08-12

Applicant: Andrew Dellow ,  Peter Bennett

Inventor： Andrew Dellow ,  Peter Bennett

IPC: G06F12/14 ,  H04N7/16 ,  G06F12/00 ,  G11C5/00

CPC classification number: G06F12/1483 ,  H04N21/443 ,  H04N21/4623

Abstract: A privileged data table maintains a list of regions of a memory which contain privileged data. When a data access operation is attempted, a privilege rule enforcer compares the address of the memory being accessed to the list of privileged regions. If the memory address falls within a privileged region, then the memory access operation is blocked unless the instruction accessing the memory has been securely authorized by a code verifier. A privileged instruction table is provided to maintain a list of instructions stored in an instruction list that have been verified. When an instruction is fetched from the instruction list, an instruction privilege identifier compares the instruction with the list of verified instructions, and generates a signal indicating the privilege status of the instruction. Instructions are blocked according to the privilege signal. Only privileged instructions are allowed to modify the privileged data table and the privileged instruction table.

Abstract translation: 特权数据表维护包含特权数据的存储器的区域列表。 当尝试进行数据访问操作时，特权规则执行者将正在访问的内存的地址与特权区域列表进行比较。 如果存储器地址落在特权区域内，则存储器访问操作被阻止，除非访问存储器的指令已被代码验证者安全地授权。 提供特权指令表以维护存储在已被验证的指令列表中的指令的列表。 当从指令列表中取出指令时，指令特权标识符将指令与验证指令的列表进行比较，并产生指示指令的特权状态的信号。 根据特权信号阻止指令。 只允许特权指令修改特权数据表和特权指令表。

公开(公告)号：US06870393B2

公开(公告)日：2005-03-22

申请号：US10406028

申请日：2003-04-02

Applicant: Deepak Agarwal

Inventor： Deepak Agarwal

IPC: H03K19/177 ,  H03K19/127

CPC classification number: H03K19/17748 ,  H03K19/17704 ,  H03K19/17736

Abstract: A field programmable device including a plurality of logic blocks; a plurality of configurable connections; at least one switching circuit; and a plurality of lines extending at least partially through the device. In a configuration mode, the switching circuit causes configuration signals to be passed to the configurable connections via the plurality of lines and in a processing mode, the plurality of lines are used in at least one of at least one logic block and at least one connection to carry data.

Abstract translation: 包括多个逻辑块的现场可编程设备; 多个可配置连接; 至少一个开关电路; 以及至少部分延伸穿过该装置的多条线。 在配置模式中，切换电路使得配置信号经由多条线路传递到可配置连接，并且在处理模式中，多条线路用于至少一个逻辑块和至少一个连接中的至少一个 携带数据。

公开(公告)号：US06865272B2

公开(公告)日：2005-03-08

申请号：US10117934

申请日：2002-04-08

Applicant: Anthony James Cole

Inventor： Anthony James Cole

IPC: H04L9/06 ,  H04L9/34 ,  H04L9/00 ,  G06F7/58

CPC classification number: H04L9/0625 ,  H04L2209/046 ,  H04L2209/12

Abstract: A method for changing the bit-order of a data value in a data processing system having a register capable of storing data strings which each comprise a plurality of sub-strings that are not individually addressable, the method comprising assigning an output data string by the steps of: loading the data value into a first data string; generating, for each sub-string of the output data string, a corresponding intermediate data string, each sub-string of which corresponds to a selected bit on the first data string and has all its bits equal to the value of the selected bit; and generating the output data string, in each sub-string of which each bit has the same value as the bits in a selected sub-string of the intermediate data string that corresponds to that sub-string of the output data string.

Abstract translation: 一种用于改变数据处理系统中的数据值的位顺序的方法，该数据处理系统具有能够存储数据串的寄存器，每个数据串包括不能单独寻址的多个子串，所述方法包括：输出数据串 步骤：将数据值加载到第一数据串中; 为输出数据串的每个子串生成相应的中间数据串，每个子串对应于第一数据串上的所选位，并且其所有位均等于所选位的值; 并且在其每个子串的每个子串中产生与对应于输出数据串的该子串的中间数据串的所选子串中的位相同的值的每个子串。

公开(公告)号：US20050040805A1

公开(公告)日：2005-02-24

申请号：US10896362

申请日：2004-07-21

Applicant: Anna Sigurdardottir

Inventor： Anna Sigurdardottir

IPC: G05F3/24 ,  G05F3/16

CPC classification number: G05F3/245

Abstract: A voltage reference circuit comprising a first reference voltage source, a second reference voltage source, at least one of said first and second reference voltage sources being dependent on temperature, and first circuitry connected to at least one of said first and second reference voltage sources to provide a third reference voltage, said third reference voltage being dependent on temperature.

Abstract translation: 一种电压参考电路，包括第一参考电压源，第二参考电压源，所述第一和第二参考电压源中的至少一个取决于温度，第一电路连接到所述第一和第二参考电压源中的至少一个， 提供第三参考电压，所述第三参考电压取决于温度。

公开(公告)号：US06842191B1

公开(公告)日：2005-01-11

申请号：US09705145

申请日：2000-11-02

Applicant: Stewart Gresty Smith

Inventor： Stewart Gresty Smith

IPC: G06T3/40 ,  G06T5/00 ,  H04N9/04 ,  H04N3/14

CPC classification number: G06T3/4015 ,  G06T5/002 ,  G06T5/003 ,  G06T5/20 ,  G06T2200/12 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/20192 ,  H04N9/045

Abstract: A video signal is produced from a color imaging array of the type having luminance elements of a first color (typically green) and chrominance elements of second and third colors (typically red and blue). The video signal processing includes, for each element of the second color, estimating a chrominance value of the third color as a function of the actual chrominance value of that element, the local neighborhood of actual chrominance values of the third color, and an anti-aliasing control value derived from the local neighborhood of actual luminance values and actual third color chrominance values. In preferred forms, a similar estimation of the second color at each third color element is performed.

Abstract translation: 从具有第一颜色（通常为绿色）的亮度元素和第二和第三颜色（通常为红色和蓝色）的色度元素的类型的彩色成像阵列产生视频信号。 视频信号处理包括：对于第二颜色的每个元素，估计作为该元素的实际色度值的函数的第三颜色的色度值，第三颜色的实际色度值的局部邻域， 从实际亮度值和实际第三色度色度值的局部邻域导出的混叠控制值。 在优选形式中，执行在每个第三颜色元素处的第二颜色的类似估计。

公开(公告)号：US20040156507A1

公开(公告)日：2004-08-12

申请号：US10705782

申请日：2003-11-10

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04L009/00

CPC classification number: H04N21/42623 ,  H04N21/26613 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，该电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 公共密钥以加密形式接收，根据每个半导体集成电路独有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。

公开(公告)号：US20040148583A1

公开(公告)日：2004-07-29

申请号：US10352799

申请日：2003-01-27

Applicant: STMicroelectronics Limited

Inventor： Andrew Hulbert ,  Enrico Gregoratto

IPC: G06F017/50

CPC classification number: G06F17/5068 ,  G06F17/505

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract translation: 布置集成电路以校正保持时间误差的方法包括：将设计中的现有单元的位置固定，确定需要校正的保持时间误差，并将缓冲单元放置在现有设计中的空格中。 通过将现有设计中的缓冲区放置在空格中，而不是在现有设计中移动单元格，可以在不改变关键路径的情况下更正保持时间。

公开(公告)号：US20040120385A1

公开(公告)日：2004-06-24

申请号：US10632566

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。