公开(公告)号：US09491015B2

公开(公告)日：2016-11-08

申请号：US14892739

申请日：2014-06-17

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H04L7/00 ,  H04L25/49 ,  H04L25/02 ,  H04B7/06

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L7/0079 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver for a three-wire digital interface, a method for operating a three-wire digital interface, a signalling system comprising the receiver, and a wireless communication device comprising the signalling system. The receiver for a three-wire digital interface comprises a first resistive element coupled between a first input terminal and a first junction node, a second resistive element coupled between a second input terminal and a second junction node, and a third resistive element coupled between a third input terminal and a third junction node. A network comprising first second and third network terminals is coupled to first, second and third junction nodes. The network has substantially the same impedance between all pairs of the first, second and third network terminals.

Abstract translation: 用于三线数字接口的接收机，用于操作三线数字接口的方法，包括接收机的信令系统以及包括信令系统的无线通信设备。 用于三线数字接口的接收机包括耦合在第一输入端和第一结节之间的第一电阻元件，耦合在第二输入端与第二结节之间的第二电阻元件， 第三输入端和第三结节点。 包括第一和第三网络终端的网络耦合到第一，第二和第三连接节点。 网络在第一，第二和第三网络终端的所有对之间具有基本上相同的阻抗。

公开(公告)号：US09478069B2

公开(公告)日：2016-10-25

申请号：US14362326

申请日：2013-01-22

Applicant: ST-Ericsson SA

Inventor： Jacob Strom ,  Jim Rasmusson ,  Gilles Ries

IPC: G06T19/20 ,  G06T17/00 ,  G06T9/00

CPC classification number: G06T19/20 ,  G06T9/00 ,  G06T17/00 ,  G06T2210/32 ,  G06T2219/2012

Abstract: A conversion between two texture compression formats comprises calculations performed at index-level for reducing handling of values with color bit-length and an amount of calculations with color values. Format conversion can thus be performed in real time upon displaying an image using the compressed texture data, without significant slowing down of a display rate of the images. It may be implemented in particular for conversion from DXT1—to ETC1 compression format, and a non-flipped or flipped orientation of an ETC1—compressed texture data block can thus be determined from said texture data block as initially compressed in DXT1 format.

Abstract translation: 两种纹理压缩格式之间的转换包括在索引级执行的计算，以减少具有颜色位长度的值的处理和带有颜色值的计算量。 因此，可以在使用压缩纹理数据显示图像时实时执行格式转换，而不会显着降低图像的显示速率。 可以特别实现用于从DXT1到ETC1压缩格式的转换，并且因此可以从DXT1格式最初压缩的所述纹理数据块确定ETC1压缩纹理数据块的非翻转或翻转取向。

公开(公告)号：US20160282418A1

公开(公告)日：2016-09-29

申请号：US15099205

申请日：2016-04-14

Applicant: ST-Ericsson SA

Inventor： Christophe Belet

IPC: G01R31/36

CPC classification number: G01R31/385 ,  G01R19/16542 ,  G01R31/36 ,  G01R31/3835 ,  G01R31/388 ,  H02J7/0047

Abstract: A process for performing an auto-test of a fully discharged battery of an electronic appliance including a battery charger, said process involving the steps of : performing an initialization phase; charging said battery with a predetermined constant current during a predefined period allowing stabilization of said current (Icurrent); detecting the voltage of said battery after said predefined period, said battery being still in charge; testing whether said sensed voltage is comprised within a predetermined range of threshold values (V1, V2), and reporting a battery failure when said sensed value is outside said range. The invention is particularly adapted to the auto-test of a backup battery made of Electric double layer capacitors or any fully discharged backup battery.

Abstract translation: 本发明特别适用于由双电层电容器或任何完全放电的备用电池制成的备用电池的自动测试。

公开(公告)号：US09436655B2

公开(公告)日：2016-09-06

申请号：US15049255

申请日：2016-02-22

Applicant: ST-ERICSSON SA, EN LIQUIDATION

Inventor： Yanmeng Sun ,  Liangliang Hu

IPC: G06F17/16 ,  G06F9/30 ,  G06F7/78 ,  G06F15/80

CPC classification number: G06F15/8061 ,  G06F7/785 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30134 ,  G06F15/8076 ,  G06F17/16

Abstract: A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.

Abstract translation: 一种用于向量存储器阵列转置的系统和方法。 该系统包括向量存储器，块转置加速器和地址控制器。 向量存储器存储向量存储器阵列。 块转置加速器读取向量存储器阵列内的数据块的向量。 块转置加速器还将数据块向量的转置写入向量存储器。 地址控制器确定向量访问顺序，并且块转置加速器根据向量存取顺序访问向量存储器阵列内的数据块的向量。

公开(公告)号：US09431905B2

公开(公告)日：2016-08-30

申请号：US14362428

申请日：2013-02-25

Applicant: ST-Ericsson SA

Inventor： Maria Francesca Seminara ,  Patrizia Milazzo ,  Salvatore Rosario Musumeci

IPC: H02M1/084 ,  H02M3/158 ,  G06F1/32 ,  H02M1/00

CPC classification number: H02M3/1584 ,  G06F1/325 ,  H02M2001/0009

Abstract: A multiphase buck converter (10) is disclosed, comprising: —a first buck converter branch (SD1, L1) comprising a first core section (COR1), a first power section (PWR1) having a first output node (LX1), a first coil (11) having a first end connected to the first output node (LX1), the first power section (PWR1) being adapted to be controlled by the first core section (COR1) for providing to the coil (L1) a coil current (I1), the first core section (COR1) and the first power section (PWR1) being integrated in a chip (IC); —a second buck converter branch (SD2, L2) comprising a second core section (COR2), a second power section (PWR2) having a second output node (LX2), a second coil (L2) having a first end connected to the second output node (LX2), the second power section (PWR2) being adapted to be controlled by the second core section (COR2) for providing to the second coil (L2) a second coil current (I2), the second core section (COR2) and the second power section (PWR2) being integrated in said chip (IC); —a feedback loop adapted to balance said coil currents (I1,I2). The feedback loop comprises a control block (C_B) that, in order to balance said coil currents, is adapted to compare a first average voltage at the first output node (LX1) with a second average voltage at the second output node (LX2) and control the first (SD1, L1) and second branch (SD2, L2) in order to make said first and second average voltages equal to each other. The control block (C_B) is integrated in said chip (IC) and has a first input directly connected to said first output node (LX1) and a second input directly connected to said second output node (LX2). The control block (C_B) is adapted to directly obtain said first and second average voltages from the instantaneous voltages of the first (LX1) and second (LX2) output nodes.

公开(公告)号：US20160127159A1

公开(公告)日：2016-05-05

申请号：US14892739

申请日：2014-06-17

Applicant: ST-ERICSSON SA

Inventor： Kimmo KOLI

IPC: H04L25/49 ,  H04B7/06

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L7/0079 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver (100) for a three-wire digital interface, comprises a first resistive element (R1) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R2) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R3) coupled between a third input terminal (C) and a third junction node (JC). A network (70) comprising first second and third network terminals (71, 72, 73) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C1) has a non-inverting input (10) coupled to the first input terminal (A), an inverting input (12) coupled to the second junction node (JB), and an output (14) coupled to a first output terminal (AJ). A second comparator (C2) has a non-inverting input (20) coupled to the AK first input terminal (A), an inverting input (22) coupled to the third junction node (JC), and an output (24) coupled to a second output terminal (AK). A third comparator (C3) has a non-inverting input (30) coupled to the second input terminal (B), an inverting input (32) coupled to the third junction node (JC), and an output (34) coupled to a third output terminal (BJ). A fourth comparator (C4) has a non-inverting input (40) coupled to the second input terminal (B), an inverting input (42) coupled to the first junction node (JA), and an output (44) coupled to a fourth output terminal (BK). A fifth comparator (C5) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input (52) coupled to the first junction node (JA), and an output (54) coupled to a fifth output terminal (CJ). A sixth comparator (C6) has a non-inverting input (60) coupled to the third input terminal (C), an inverting input (62) coupled to the second junction node (JB), and an N output (64) coupled to a sixth output terminal (CK).

公开(公告)号：US09306631B2

公开(公告)日：2016-04-05

申请号：US14443680

申请日：2013-11-21

Applicant: ST-Ericsson SA

Inventor： Achraf Dhayni

IPC: H04B5/00 ,  H04W4/00

CPC classification number: H04B5/0031 ,  H04B5/0081 ,  H04W4/80

Abstract: A method of conditioning a first signal transmitted between a first and a second near field communication, NFC, device, the method comprising: determining a transfer function representative of a distortion arising from transfer of a signal from the first NFC device to the second NFC device; determining a pre-distortion function from the transfer function; and applying the pre-distortion function to the first signal, wherein the pre-distortion function at least partially compensates for the determined transfer function.

Abstract translation: 一种调节在第一和第二近场通信NFC装置之间传输的第一信号的方法，所述方法包括：确定代表从第一NFC设备传送到第二NFC设备的信号所产生的失真的传递函数 ; 从传递函数确定预失真函数; 以及将所述预失真函数应用于所述第一信号，其中所述预失真函数至少部分地补偿所确定的传递函数。

公开(公告)号：US09306505B2

公开(公告)日：2016-04-05

申请号：US14343894

申请日：2012-10-08

Applicant: ST-Ericsson SA

Inventor： Frederic Rivoirard

IPC: H03F3/04 ,  H03F1/32 ,  H03F1/26 ,  H03F1/56 ,  H03F3/195 ,  H03F3/45 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/3205 ,  H03F1/26 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/45273 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45091 ,  H03F2203/45306 ,  H03F2203/45311 ,  H03F2203/45312 ,  H03F2203/45334 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45576

Abstract: A low-noise amplifier (LNA) circuit utilizes the capacitive cross coupling technique with two pairs of NMOS transistors in conjunction with two cross coupled PMOS transistors to obtain a reduced noise figure. By using the cross coupling technique on the PMOS input transistor, the LNA circuit is able to reduce the noise figure below 2 dB without the use of an inductor. This LNA circuit may be used to amplify a signal in the WLAN band or the Bluetooth band, either independently or simultaneously.

Abstract translation: 低噪声放大器（LNA）电路利用电容交叉耦合技术与两对NMOS晶体管结合两个交叉耦合的PMOS晶体管来获得降低的噪声系数。 通过在PMOS输入晶体管上使用交叉耦合技术，LNA电路能够将低于2 dB的噪声系数降低，而无需使用电感器。 该LNA电路可以用于单独地或同时地放大WLAN频带或蓝牙频带中的信号。

公开(公告)号：US09287874B2

公开(公告)日：2016-03-15

申请号：US14655353

申请日：2013-12-05

Applicant: ST-Ericsson SA

Inventor： Pierangelo Confalonieri ,  Federico Guanziroli

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K19/01714

Abstract: A voltage level shifting device for driving a capacitive load has an input terminal for receiving a first input signal switchable between a first logic state corresponding to a first reference voltage and a second logic state corresponding to a second reference voltage, and an output terminal for supplying an output signal switchable between a first logic state corresponding to a third reference voltage and a second logic state corresponding to a fourth reference voltage. The device also has a first electronic circuit that is activated following a commutation of the first input signal from the first reference voltage to the second reference voltage for fixing the output terminal to the fourth reference voltage. The device further has a second electronic circuit that is activated following a commutation of the first input signal from the second reference voltage to the first reference voltage.

Abstract translation: 用于驱动电容性负载的电压电平移动装置具有用于接收可在与第一参考电压相对应的第一逻辑状态和对应于第二参考电压的第二逻辑状态之间切换的第一输入信号的输入端和用于提供 输出信号可在对应于第三参考电压的第一逻辑状态与对应于第四参考电压的第二逻辑状态之间切换。 该装置还具有第一电子电路，其在从第一参考电压到第二参考电压的第一输入信号的换向之后被激活，用于将输出端固定到第四参考电压。 该装置还具有第二电子电路，其在从第二参考电压到第一参考电压的第一输入信号的换向之后被激活。

公开(公告)号：US20160063680A1

公开(公告)日：2016-03-03

申请号：US14782013

申请日：2014-04-14

Applicant: ST-ERICSSON SA

Inventor： Gilles RIES

IPC: G06T3/60 ,  G09G5/395

CPC classification number: G06T3/60 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/0492

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

Abstract translation: 一种方法允许在图像的像素值从应用输出存储器连续地传送到显示单元的同时，将图像光栅方向从应用光栅方向改变到屏幕光栅方向。 在应用输出存储器和显示单元之间实现单个缓冲存储器阵列。 依次使用缓冲存储器阵列的单元的两个写入顺序，每个写入顺序与单元的不同读取顺序组合。 该方法可以是硬件实现的，并且适用于像素值的突发处理。