Locked loop circuit with reference signal provided by un-trimmed oscillator

    公开(公告)号:US10862487B2

    公开(公告)日:2020-12-08

    申请号:US16674207

    申请日:2019-11-05

    Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

    Capturing a stable image using an ambient light sensor-based trigger

    公开(公告)号:US10855912B2

    公开(公告)日:2020-12-01

    申请号:US16030572

    申请日:2018-07-09

    Inventor: Rosarium Pila

    Abstract: A method and apparatus for capturing stable images are disclosed. An ambient light sensor makes measurements of ambient light. A change in ambient light between two measurements is determined. If the change in ambient light measurements falls in a predefined range, then the change may be attributable to ambient light sensor being blocked by a user to trigger image capturing. Consequently, a camera is triggered to capture an image. Conversely, if the change in ambient light measurement is outside the range, image capturing is not triggered as the change may be attributable to other factors.

    TRANSCONDUCTANCE BOOSTED CASCODE COMPENSATION FOR AMPLIFIER

    公开(公告)号:US20200343869A1

    公开(公告)日:2020-10-29

    申请号:US16829088

    申请日:2020-03-25

    Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

    CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT CONDITION IN A MEMORY CIRCUIT

    公开(公告)号:US20200342940A1

    公开(公告)日:2020-10-29

    申请号:US16846938

    申请日:2020-04-13

    Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.

    AUTOMATIC GAIN CONTROL FOR A RECEIVER
    236.
    发明申请

    公开(公告)号:US20200313708A1

    公开(公告)日:2020-10-01

    申请号:US16825887

    申请日:2020-03-20

    Inventor: Gagan Midha

    Abstract: An automatic gain controller for a receiver analog frontend is provided. The automatic gain controller sets a plurality of gains for a plurality of analog frontend stages, respectively. The automatic gain controller detects a first signal level at an output of the analog frontend, determines that the first signal level is saturated and sets a first gain of a first analog frontend stage of the plurality of analog frontend stages to a first coarse gain value based on the first signal level. In response to setting the first gain, the automatic gain controller detects a second signal level at the output of the analog frontend, determines whether the second signal level is saturated and on a condition that the second signal level is not saturated, sets the first gain of the first analog frontend stage to a first fine gain value based on the second signal level.

    SQUELCH DETECTION DEVICE
    237.
    发明申请

    公开(公告)号:US20200274504A1

    公开(公告)日:2020-08-27

    申请号:US16746518

    申请日:2020-01-17

    Inventor: Prashant Singh

    Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.

    TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A FAULT ENABLE GENERATION CIRCUIT WITHIN THE MEMORY

    公开(公告)号:US20200219579A1

    公开(公告)日:2020-07-09

    申请号:US16702744

    申请日:2019-12-04

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

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