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    Method and apparatus for end-to-end ATM calls based on the interworking of ATM switched virtual circuit signaling with Q.2630.1 AAL2 signaling
    242.
    发明授权
    Method and apparatus for end-to-end ATM calls based on the interworking of ATM switched virtual circuit signaling with Q.2630.1 AAL2 signaling 失效
    基于ATM交换虚拟电路信令与Q.2630.1 AAL2信令的互通的端到端ATM呼叫的方法和装置

    公开(公告)号：US07065093B1

    公开(公告)日：2006-06-20

    申请号：US09859865

    申请日：2001-05-17

    Applicant: Rajesh Kumar ,  Mohamed Saad-Eldin Mostafa ,  John Gwilym Ellis

    Inventor： Rajesh Kumar ,  Mohamed Saad-Eldin Mostafa ,  John Gwilym Ellis

    IPC: H04L12/28

    CPC classification number: H04L41/0896

    Abstract: Methods and apparatus are disclosed for end-to-end ATM calls based on the interworking of ATM SVC signaling (such as private network-network interface signaling) with A.2630.1 AAL2 signaling. In one network, Q.2630.1 AAL2 signaling in the originating access segment triggers, on proper authentication, ATM SVC signaling (e.g., PNNI, IISP, AINI, etc.) in the core, which triggers Q.2630.1 AAL2 signaling in the terminating access segment. The triggering is done at the edge-core boundary where an AAL2 switch and/or multiplexer or an ATM switch with AAL2 multiplexing/switching capabilities is located. In the access network between the ATM-AAL2 edge switch and the edge gateway, multiplexed AAL2 virtual channel connections (VCCs) are typically used. Single-CID AAL2 SVCs are typically used in the core network, and between the ATM-AAL2 edge switch and PSTN trunk gateways. The binding of voice calls to ATM bearer channels is done at the edge gateway when triggered by a call agent.

    Abstract translation: 基于与A.2630.1 AAL2信令的ATM SVC信令（例如专用网络 - 网络接口信令）的互通，公开了用于端到端ATM呼叫的方法和装置。 在一个网络中，起始接入段中的Q.2630.1 AAL2信令在正确认证中触发核心中的ATM SVC信令（例如，PNNI，IISP，AINI等），这触发Q.2630.1终止接入中的AAL2信令 分割。 触发在边缘核心边界完成，其中AAL2开关和/或多路复用器或具有AAL2复用/切换能力的ATM交换机位于其中。 在ATM-AAL2边缘交换机和边缘网关之间的接入网络中，通常使用多路复用的AAL2虚拟通道连接（VCC）。 单CID AAL2 SVC通常用于核心网络，ATM-AAL2边缘交换机和PSTN中继网关之间。 语音呼叫与ATM承载信道的绑定是在呼叫代理触发时在边缘网关完成的。

    Silicon carbide semiconductor device and method of fabricating the same
    246.
    发明授权
    Silicon carbide semiconductor device and method of fabricating the same 有权

    公开(公告)号：US06551865B2

    公开(公告)日：2003-04-22

    申请号：US10107174

    申请日：2002-03-28

    Applicant: Rajesh Kumar ,  Hiroki Nakamura ,  Jun Kojima

    Inventor： Rajesh Kumar ,  Hiroki Nakamura ,  Jun Kojima

    IPC: H01L21332

    CPC classification number: H01L29/8083 ,  H01L29/1608 ,  Y10S438/931

    Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

    Pulsed circuit topology including a pulsed, domino flip-flop
    247.
    发明授权
    Pulsed circuit topology including a pulsed, domino flip-flop 失效
    脉冲电路拓扑包括脉冲多米诺触发器

    公开(公告)号：US06496038B1

    公开(公告)日：2002-12-17

    申请号：US09608857

    申请日：2000-06-30

    Applicant: Milo D. Sprague ,  Rajesh Kumar ,  Robert J. Murray

    Inventor： Milo D. Sprague ,  Rajesh Kumar ,  Robert J. Murray

    IPC: H03K19096

    CPC classification number: H03K19/0963 ,  H03K5/1534

    Abstract: A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

    Abstract translation: 包括脉冲多米诺触发器的脉冲电路拓扑。 电路包括具有在评估脉冲期间响应于输入数据的多米诺骨牌输出节点的多米诺骨牌逻辑门。 复位电路启动并自动终止多米诺骨牌输出节点预充电的复位脉冲。 提供响应于第一脉冲时钟输入信号的锁存器来锁存在多米诺骨牌输出节点处指示的数据。

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