公开(公告)号：US20210089875A1

公开(公告)日：2021-03-25

申请号：US16576533

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/56 ,  G06F17/16 ,  G11C11/54

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US10956814B2

公开(公告)日：2021-03-23

申请号：US16182237

申请日：2018-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G06N3/08 ,  G06F3/06 ,  G06F17/16

Abstract: Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network. The components within the configurable hardware system that are configurable can include vector-by-matrix multiplication arrays, summer circuits, activation circuits, inputs, reference devices, neurons, and testing circuits. These devices can be configured to provide various layers or vector-by-matrix multiplication arrays of various sizes, such that the same hardware can be used in analog neural memory systems with different requirements.

公开(公告)号：US20200272886A1

公开(公告)日：2020-08-27

申请号：US16746837

申请日：2020-01-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G11C16/30 ,  G11C16/08

Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.

公开(公告)号：US10748630B2

公开(公告)日：2020-08-18

申请号：US15826345

申请日：2017-11-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Steven Lemke ,  Santosh Hariharan ,  Stanley Hong

IPC: G11C16/10 ,  G11C16/34

Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.

公开(公告)号：US20200243139A1

公开(公告)日：2020-07-30

申请号：US16382060

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C14/00 ,  G11C11/54 ,  G06N3/04

Abstract: A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

公开(公告)号：US10720217B1

公开(公告)日：2020-07-21

申请号：US16382060

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/54 ,  G06N3/04 ,  G11C14/00 ,  H01L27/11521

Abstract: A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

公开(公告)号：US10699787B2

公开(公告)日：2020-06-30

申请号：US16783286

申请日：2020-02-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/788 ,  H01L29/423

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

公开(公告)号：US10692548B2

公开(公告)日：2020-06-23

申请号：US16551593

申请日：2019-08-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

IPC: G11C16/06 ,  G11C7/10 ,  G11C8/12 ,  H01L27/11521 ,  H01L21/28 ,  G11C16/08 ,  G11C29/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C29/12 ,  H01L27/11524

Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

公开(公告)号：US10658027B2

公开(公告)日：2020-05-19

申请号：US15002302

申请日：2016-01-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

IPC: H01L29/76 ,  G11C11/419 ,  G11C16/04 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

公开(公告)号：US20200065660A1

公开(公告)日：2020-02-27

申请号：US16182237

申请日：2018-11-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G06F17/16 ,  G06F3/06 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network. The components within the configurable hardware system that are configurable can include vector-by-matrix multiplication arrays, summer circuits, activation circuits, inputs, reference devices, neurons, and testing circuits. These devices can be configured to provide various layers or vector-by-matrix multiplication arrays of various sizes, such that the same hardware can be used in analog neural memory systems with different requirements.