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    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
    242.
    发明授权
    System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory 有权

    公开(公告)号：US10699787B2

    公开(公告)日：2020-06-30

    申请号：US16783286

    申请日：2020-02-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/788 ,  H01L29/423

    Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

    High density split-gate memory cell
    244.
    发明授权
    High density split-gate memory cell 有权

    公开(公告)号：US10658027B2

    公开(公告)日：2020-05-19

    申请号：US15002302

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

    IPC: H01L29/76 ,  G11C11/419 ,  G11C16/04 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array
    249.
    发明申请
    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array 审中-公开

    公开(公告)号：US20190295647A1

    公开(公告)日：2019-09-26

    申请号：US16015020

    申请日：2018-06-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

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