公开(公告)号：US07319722B2

公开(公告)日：2008-01-15

申请号：US10039233

申请日：2001-12-31

Applicant: Hervé Cassagnes

Inventor： Hervé Cassagnes

IPC: H04L27/10

CPC classification number: H04L25/4904

Abstract: A decoding circuit and associated method are provided for decoding a biphase signal. The decoding circuit may include a precharging register to precharge a pair of states of the biphase signal, where a state of the pair of states is precharged at each pulse of a periodic precharging signal. The decoding circuit may further include a verification circuit to compare the two states of the pair of states and give an active error signal if the two states are equal.

Abstract translation: 提供了解码电路和相关联的方法来解码双相信号。 解码电路可以包括预充电寄存器，用于对双相信号的一对状态进行预充电，其中一对状态的状态在周期性预充电信号的每个脉冲处被预充电。 解码电路还可以包括验证电路，以比较两对状态的两个状态，并且如果两个状态相等则给出有效的误差信号。

公开(公告)号：US20070294517A1

公开(公告)日：2007-12-20

申请号：US11567998

申请日：2006-12-07

Applicant: Renaud Ayrignac ,  Isabelle Sename

Inventor： Renaud Ayrignac ,  Isabelle Sename

IPC: G06F9/30

CPC classification number: G06F9/4812 ,  G06F9/30043 ,  G06F9/3861

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract translation: 本公开涉及一种用于由处理器执行用于保存/恢复处理器的多个内部寄存器的指令的方法。 该方法包括分解保存/恢复指令以产生用于保存/恢复寄存器的内容的微指令，执行每个微指令，初始化寄存器的保存/恢复进度状态，更新进度状态 在每次生成用于保存/恢复寄存器的微指令时的保存/恢复，在保存/恢复寄存器的中断的情况下保存进度状态以执行更高优先级的任务，并恢复进度 恢复寄存器的保存/恢复时的状态。

公开(公告)号：US20070252177A1

公开(公告)日：2007-11-01

申请号：US11740881

申请日：2007-04-26

Applicant: Robert Cuchet ,  Sebastien Pruvost

Inventor： Robert Cuchet ,  Sebastien Pruvost

IPC: H01L29/80

CPC classification number: H01L23/66 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/00

Abstract: The invention relates to integrated circuits for microwave applications in the millimeter wavelength range (frequencies of around 50 GHz). To improve the performance of the microwave transmission lines in the circuit, a structure of conducting vias between a transmission line and a conducting zone is proposed. The vias are formed in apertures in a benzocyclobutene layer. These apertures are larger at their base than the conducting zones. The transmission line descends into the aperture but does not come back up over the edges of the aperture. The parasitic capacitances with the substrate at the point of contact are minimized.

Abstract translation: 本发明涉及用于在毫米波长范围内的微波应用的集成电路（约50GHz的频率）。 为了提高电路中的微波传输线的性能，提出了传输线与导电区之间的通孔结构。 通孔形成在苯并环丁烯层的孔中。 这些孔在其基部比导电区域更大。 传输线下降到光圈中，但不会在光圈的边缘上恢复。 在接触点处的衬底的寄生电容最小化。

公开(公告)号：US07280156B2

公开(公告)日：2007-10-09

申请号：US10741424

申请日：2003-12-19

Applicant: Frederic Roelens

Inventor： Frederic Roelens

IPC: H04N9/475

CPC classification number: H04N21/4307 ,  H04N21/4341

Abstract: A method and device are provided for synchronizing the presentation of audio frames and/or of video frames comprises the detection of presentation time stamps in a stream of frames. The presentation instant indicated by a time stamp is compared with a time delivered by a local reference clock. Depending on a variance and on an average of values of deviation between presentation instants and corresponding times indicated by the clock, the clock can be initialized according to the presentation instant indicated by a time stamp or the presentation of the frames can be adjusted.

Abstract translation: 提供了一种用于使音频帧和/或视频帧的呈现同步的方法和装置包括检测帧流中的呈现时间戳。 由时间戳表示的演示时刻与由本地参考时钟传递的时间进行比较。 根据方差和表示时刻之间的偏差值与时钟指示的相应时间的平均值，可以根据时间戳表示的显示时刻初始化时钟，或者可以调整帧的呈现。

公开(公告)号：US20070234156A1

公开(公告)日：2007-10-04

申请号：US11673911

申请日：2007-02-12

Applicant: Frederic Bancel ,  David Hely

Inventor： Frederic Bancel ,  David Hely

IPC: G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/31719

Abstract: An electronic circuit includes configurable cells with a test input and an output. The configurable cells are capable of being connected to one another in a chain in a predefined order via the test inputs and the outputs to form a test shift register if they receive a chaining command signal. A connection control module disconnects the test input from at least one configurable cell if the connection control module receives an invalid identification key. The connection control module leaves disconnected the test input from the at least one configurable cell, or applies a constant potential on the test input of the at least one configurable cell, or connects the test input of the at least one configurable cell at an output of a random-data generator.

Abstract translation: 电子电路包括具有测试输入和输出的可配置单元。 可配置单元能够经由测试输入和输出以预定义的顺序彼此连接，以形成测试移位寄存器，如果它们接收到链接命令信号。 如果连接控制模块接收到无效的识别密钥，则连接控制模块将测试输入与至少一个可配置单元断开连接。 连接控制模块将测试输入从至少一个可配置单元断开，或者在至少一个可配置单元的测试输入上施加恒定电位，或将至少一个可配置单元的测试输入连接到 随机数据生成器。

公开(公告)号：US07274252B2

公开(公告)日：2007-09-25

申请号：US11066604

申请日：2005-02-25

Applicant: Alexandre Pujol ,  Colette Morche

Inventor： Alexandre Pujol ,  Colette Morche

IPC: G06G7/26

CPC classification number: H03F3/3069 ,  H03F3/30

Abstract: A power amplifier circuit comprising first and second modules, a current source and a push-pull module. The push-pull module comprises two intermediate transistors and two output transistors. The circuit also comprises third and fourth modules, operating in current mirror mode. Inputs of the third module are respectively connected to one main electrode of one of the intermediate transistors and to a node internal to the first module. Outputs of the fourth module are respectively connected to a main electrode of the other intermediate transistor and to a node internal to the second module. The circuit is designed to form a power output stage of an operational amplifier.

Abstract translation: 一种功率放大器电路，包括第一和第二模块，电流源和推挽模块。 推挽模块包括两个中间晶体管和两个输出晶体管。 电路还包括以当前镜像模式工作的第三和第四模块。 第三模块的输入分别连接到中间晶体管之一的一个主电极和第一模块内部的节点。 第四模块的输出分别连接到另一个中间晶体管的主电极和连接到第二模块内部的节点。 该电路被设计成形成运算放大器的功率输出级。

公开(公告)号：US20070220331A1

公开(公告)日：2007-09-20

申请号：US11671661

申请日：2007-02-06

Applicant: Renaud Ayrignac ,  Xavier Robert

Inventor： Renaud Ayrignac ,  Xavier Robert

IPC: G06F11/00

CPC classification number: G06F11/3656

Abstract: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging interface which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface comprising internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface comprises a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and access means for transferring a datum between the resource selected and a data field accessible by the processing unit.

Abstract translation: 所公开的系统和方法涉及包括处理单元和调试接口的处理器，该接口可连接到外部仿真器，用于调试由处理器执行的程序，该调试接口包括外部仿真器至少部分可访问的内部资源。 根据一个实施例，调试接口包括选择电路，用于根据由处理单元提供的参考来选择调试接口的内部资源;以及访问装置，用于在所选择的资源和可访问的数据字段之间传送数据; 处理单元。

公开(公告)号：US20070218649A1

公开(公告)日：2007-09-20

申请号：US11748995

申请日：2007-05-15

Applicant: Caroline Hernandez

Inventor： Caroline Hernandez

IPC: H01L21/461 ,  H01L21/46

CPC classification number: H01L21/6835 ,  H01L21/78 ,  H01L25/50 ,  H01L31/18 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a first semiconductor wafer having a first surface and a second surface, by placing, on the second surface of the first wafer, a second wafer with an interposed resist layer, and thinning down the first surface of the first semiconductor wafer.

Abstract translation: 一种用于处理具有第一表面和第二表面的第一半导体晶片的方法，通过在第一晶片的第二表面上放置具有插入的抗蚀剂层的第二晶片，并且使第一半导体晶片的第一表面变薄。

公开(公告)号：US20070216464A1

公开(公告)日：2007-09-20

申请号：US11713469

申请日：2007-03-01

Applicant: Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

Inventor： Philippe Roche ,  Francois Jacquet ,  Jean-Jacques De Jong

IPC: G06F1/04

CPC classification number: H03K19/00338 ,  G06F1/10 ,  G06F1/24 ,  H03K5/1506

Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.

Abstract translation: 本发明的一个实施例涉及一种用于分发初始信号的电路，包括接收初始信号的输入节点，每个向电路组件提供至少一个结果信号的多个终端节点，以及输入节点和 连接多个中间节点的多个终端节点，其中连接分支被复制，使得输入节点和中间节点之间的每个节点包括两个输入和两个输出，允许初始信号向终端双重传播 节点通过重复连接分支，每个终端节点终端节点接收两个输入信号，初始信号的图像并提供所得到的初始信号：如果所述输入信号相同或不活动，则输入信号的图像如果输入信号不同 从彼此。

公开(公告)号：US20070211520A1

公开(公告)日：2007-09-13

申请号：US11706865

申请日：2007-02-14

Applicant: Laurent Dedieu ,  Sebastien Lefebvre

Inventor： Laurent Dedieu ,  Sebastien Lefebvre

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H03K3/356008 ,  H03K3/356104

Abstract: An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract translation: 本发明的一个实施例涉及一种用于存储存储器位的装置，其具有互补的第一和第二读/写端子的双稳态电路，其中所述器件包括连接到所述双稳态电路的初始化输入，所述输入被设计为去 控制所述双稳态电路的预加载阶段并遵循所述预加载阶段的第一状态进入控制在所述读/写端子处所述存储器位及其补码的设置的第二状态。