公开(公告)号：US20090198276A1

公开(公告)日：2009-08-06

申请号：US12364424

申请日：2009-02-02

Applicant: Young-Jun Lee

Inventor： Young-Jun Lee

IPC: A61F5/00

CPC classification number: A61F5/0193 ,  A61F5/01

Abstract: A pelvic balancer is disclosed. The pelvic balancer includes a first correction part to support any one of user's left and right pelvic bones placed thereon, a second correction part to support the other one of the user's left and right pelvic bones placed thereon, and a central shaft connected with the first correction part and the second correction part so that the first correction part and the second correction part can rotate. Accordingly, pelvis correction can be achieved by setting a dislocated pelvis to a normal position only by using a user's weight without application of a physical pressing force.

Abstract translation: 公开了一种骨盆平衡器。 骨盆平衡器包括：第一校正部，用于支撑放置在其上的使用者的左右骨盆骨骼中的任一个;第二校正部，用于支撑放置在其上的使用者的左右骨盆骨中的另一个，以及与第一 校正部和第二校正部，使得第一校正部和第二校正部能够旋转。 因此，仅通过在不施加物理按压力的情况下使用使用者的体重来将脱位的骨盆设置到正常位置即可实现骨盆修正。

公开(公告)号：US07563667B2

公开(公告)日：2009-07-21

申请号：US12002241

申请日：2007-12-13

Applicant: Choul Joo Ko ,  Yong Jun Lee

Inventor： Choul Joo Ko ,  Yong Jun Lee

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L28/40

Abstract: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

Abstract translation: 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

公开(公告)号：US20090156236A1

公开(公告)日：2009-06-18

申请号：US12337088

申请日：2008-12-17

Applicant: Sung-Beom JUNG ,  Jae-Yeong KWON ,  Soo-Yeul OH ,  Pyeong-Hwan WEE ,  Sang-Jun LEE ,  Young-Hak CHOI ,  Sang-Ho LEE

Inventor： Sung-Beom JUNG ,  Jae-Yeong KWON ,  Soo-Yeul OH ,  Pyeong-Hwan WEE ,  Sang-Jun LEE ,  Young-Hak CHOI ,  Sang-Ho LEE

IPC: H04W68/00 ,  H04B17/00

CPC classification number: H04W60/04 ,  H04B17/318 ,  H04W68/00

Abstract: An apparatus and method for determining operation of location update in a broadband wireless communication system are provided. The apparatus includes a receiver, an interpreter, and a determiner. In an idle mode, the receiver receives a paging advertisement message from a Base Station (BS). The interpreter identifies paging group identification information included in the paging advertisement message. The determiner determines one of execution and non-execution of a location update process due to a change of a paging group if the paging group identification information is different from paging group identification information included in a previously received paging advertisement message.

Abstract translation: 提供了一种用于确定宽带无线通信系统中的位置更新操作的装置和方法。 该装置包括接收器，解释器和确定器。 在空闲模式中，接收机从基站（BS）接收寻呼广告消息。 解释器识别寻呼广告消息中包括的寻呼组标识信息。 如果寻呼组识别信息不同于先前接收的寻呼广告消息中包括的寻呼组标识信息，则由于寻呼组的改变，确定器确定位置更新过程的执行和不执行之一。

公开(公告)号：US20090140320A1

公开(公告)日：2009-06-04

申请号：US12275369

申请日：2008-11-21

Applicant: Seung-Jun LEE ,  Woon-Kyung LEE

Inventor： Seung-Jun LEE ,  Woon-Kyung LEE

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Abstract translation: 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US20090137073A1

公开(公告)日：2009-05-28

申请号：US12360444

申请日：2009-01-27

Applicant: Ho Joon PARK ,  Woong Lin Hwang ,  Seog Moon Choi ,  Sung Jun Lee ,  Sang Hyun Choi ,  Chang Hyun Lim

Inventor： Ho Joon PARK ,  Woong Lin Hwang ,  Seog Moon Choi ,  Sung Jun Lee ,  Sang Hyun Choi ,  Chang Hyun Lim

IPC: H01L33/00

CPC classification number: H01L33/641 ,  H01L33/46 ,  H01L2224/16225 ,  H01L2224/97

Abstract: The present invention provides an LED package and the fabrication method thereof. The present invention provides an LED package including a submount silicon substrate and insulating film and electrode patterns formed on the submount silicon substrate. The LED package also includes a spacer having a through hole, formed on the electrode patterns. The LED package further includes an LED received in the through hole, flip-chip bonded to the electrode patterns, and an optical element attached to the upper surface of the spacer.

Abstract translation: 本发明提供一种LED封装及其制造方法。 本发明提供了一种LED封装，其包括基座硅基板和绝缘膜以及形成在基座硅基板上的电极图案。 LED封装还包括形成在电极图案上的具有通孔的间隔物。 LED封装还包括接收在通孔中的LED，与芯片连接的倒装芯片，以及附着到间隔物的上表面的光学元件。

公开(公告)号：US20090122596A1

公开(公告)日：2009-05-14

申请号：US12073678

申请日：2008-03-07

Applicant: In-Jun Hwang ,  Hyung-soon Shin ,  Seung-Jun Lee ,  Sun-ae Seo ,  Kee-won Kim ,  Kwang-seok Kim

Inventor： In-Jun Hwang ,  Hyung-soon Shin ,  Seung-Jun Lee ,  Sun-ae Seo ,  Kee-won Kim ,  Kwang-seok Kim

IPC: G11C11/14

CPC classification number: G11C11/1697 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

Abstract: Provided are a semiconductor memory device and a method of programming the same. The semiconductor memory device includes a mode input value generating unit and a logic operating unit. The mode input value generating unit changes a connection state between input values of a current driving circuit so as to correspond to each of at least two operating modes, and defines a logic function of a magnetic memory cell connected to the current driving circuit in response to each operating mode. The logic operating unit performs a logic operation on the logic functions of at least two magnetic memory cells defined according to each of the operating modes and generates a result of logic operation.

Abstract translation: 提供一种半导体存储器件及其编程方法。 半导体存储器件包括模式输入值生成单元和逻辑运算单元。 模式输入值生成单元将当前驱动电路的输入值之间的连接状态改变为对应于至少两个操作模式中的每一个，并且响应于所述至少两个操作模式定义连接到当前驱动电路的磁存储单元的逻辑功能 每个操作模式。 逻辑操作单元对根据每个操作模式定义的至少两个磁存储器单元的逻辑功能进行逻辑运算，并产生逻辑运算的结果。

公开(公告)号：US07514741B2

公开(公告)日：2009-04-07

申请号：US11491194

申请日：2006-07-24

Applicant: Seung-Jun Lee ,  Dong-Gyun Han

Inventor： Seung-Jun Lee ,  Dong-Gyun Han

IPC: H01L27/115

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A nonvolatile memory device and a method for fabricating the nonvolatile memory device are disclosed. The method comprises forming a device isolation pattern comprising a first opening and a second opening wider than the first opening, wherein the first opening is formed in the second opening; and forming a gate insulating layer on a first portion of an active region of the substrate, wherein the first opening exposes the first portion of the active region of the substrate. The method further comprises forming a first conductive layer in the first and second openings and on the gate insulating layer, partially etching the first conductive layer to form a U-shaped floating gate electrode, forming a gate interlayer insulating layer on the U-shaped floating gate electrode, forming a second conductive layer on the gate interlayer insulating layer and the device isolation pattern, and patterning the second conductive layer.

Abstract translation: 公开了非易失性存储器件和非易失性存储器件的制造方法。 该方法包括形成包括第一开口和比第一开口更宽的第二开口的装置隔离图案，其中第一开口形成在第二开口中; 以及在所述衬底的有源区的第一部分上形成栅极绝缘层，其中所述第一开口暴露所述衬底的有源区的第一部分。 该方法还包括在第一和第二开口中以及在栅极绝缘层上形成第一导电层，部分蚀刻第一导电层以形成U形浮栅，在U形浮动上形成栅极层间绝缘层 栅电极，在栅极层间绝缘层上形成第二导电层和器件隔离图案，并对第二导电层进行构图。

公开(公告)号：US20090089556A1

公开(公告)日：2009-04-02

申请号：US12265011

申请日：2008-11-05

Applicant: Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

Inventor： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

IPC: G06F9/305

CPC classification number: G06F7/22 ,  G06F7/544 ,  H03M13/395 ,  H03M13/4107

Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

Abstract translation: 用于维特比解码器或turbo解码器的高速加法比较选择（ACS）电路具有比使用传统ACS电路可实现的更低的关键路径延迟。 根据本发明的一个实施例，路径和分支度量被分成最重要和最不重要的部分，这些部分被分开地添加以减少传播延迟。

公开(公告)号：US20090079173A1

公开(公告)日：2009-03-26

申请号：US12283061

申请日：2008-09-09

Applicant: Myung-ryun Jang ,  Byoung-sun Yoo ,  Tae-woo Kim ,  Dong-jun Lee ,  Eun-hwan Oh ,  Kyun-soon Choi

Inventor： Myung-ryun Jang ,  Byoung-sun Yoo ,  Tae-woo Kim ,  Dong-jun Lee ,  Eun-hwan Oh ,  Kyun-soon Choi

IPC: B60R21/20

CPC classification number: B60R21/213 ,  Y10T24/30 ,  Y10T24/47

Abstract: There is provided a bracket for securing a side airbag for an automotive vehicle. The bracket includes a support plate, an installation plate positioned at upper part of the support plate and including an installation aperture, and fixing plates formed by being forwardly bent from the right and left edges, with respect to the installation plate, of the support plate.

Abstract translation: 提供了用于固定用于机动车辆的侧面安全气囊的支架。 支架包括支撑板，位于支撑板的上部并且包括安装孔的安装板，以及相对于安装板从支撑板的左右边缘向前弯曲形成的固定板 。

公开(公告)号：US07491978B2

公开(公告)日：2009-02-17

申请号：US11492754

申请日：2006-07-26

Applicant: Alexander L'Vovich Zakgeym ,  Seog Moon Choi ,  Sung Jun Lee

Inventor： Alexander L'Vovich Zakgeym ,  Seog Moon Choi ,  Sung Jun Lee

IPC: H01L33/00

CPC classification number: H01L33/62 ,  H01L2224/16

Abstract: A light emitting diode package is provided. The light emitting diode package comprises a submount substrate which includes a mounting region having side walls inclined upwardly, first and second cavities formed around the mounting region, and first and second grooves extending between the mounting region and the first and second cavities on an upper surface of the submount. The package further comprises first and second bump pads formed on a bottom surface of the mounting surface, first and second bonding pads formed on a bottom surface of the first and second cavities, respectively, first and second conductive lines formed along a bottom surface of the first and second grooves for connecting the first and second bump pads to the first and second bonding pads, respectively, and a light emitting diode mounted on the mounting region so as to be connected to the first and second bump pads.

Abstract translation: 提供发光二极管封装。 发光二极管封装包括副安装座基板，其包括具有向上倾斜的侧壁的安装区域，围绕安装区域形成的第一和第二空腔，以及在安装区域与第一和第二空腔之间在上表面上延伸的第一和第二凹槽 的下层。 该封装还包括形成在安装表面的底表面上的第一和第二凸块焊盘，分别形成在第一和第二腔的底表面上的第一和第二焊盘，沿着第一和第二焊盘的底表面形成的第一和第二导电线 用于将第一和第二凸块焊盘分别连接到第一和第二接合焊盘的第一和第二凹槽以及安装在安装区域上以便连接到第一和第二凸块焊盘的发光二极管。